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參數(shù)資料
| 型號： | MB90F57APMT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 106/133頁 |
| 文件大?。?/td> | 2509K |
| 代理商： | MB90F57APMT |
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MB90570 Series
74
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit and flag are prepared for each register.
If the value set in the address detection register matches an address and if the interrupt enable bit is set at “1”,
the interrupt flag is set at “1” and the instruction code loaded into the CPU is replaced forcibly with the INT9
instruction code. The interrupt flag is cleared to “0” by writing “0” by an instruction.
(1) Register Configuration
Program address detection register 0 to 2 (PADR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
R/W : Readable and writable
—: Reserved
X : Undefined
Address
PADR0 (Low order address) : 001FF0H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
Address
PADR0 (Middle order address) : 001FF1H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
Address
PADR0 (High order address) : 001FF2H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
Address
PADR1 (Low order address) : 001FF3H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
Address
PADR1 (Middle order address) : 001FF4H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
Address
PADR1 (High order address) : 001FF5H
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
Address
00009EH
—
R/W
Program address detection register 3 to 5 (PADR1)
Program address detection control status register (PACSR)
RESV
AD1E
AD1D
AD0E
AD0D
RESV : Reserved bit
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