參數(shù)資料
型號： MB90F562BPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 44/92頁
文件大?。?/td> 2097K
代理商： MB90F562BPMC
MB90560/565 Series
DS07-13715-5E
49
8.
Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this
hardware interrupt can be specified by software.
Delayed interrupt generation module functions
Block diagram
Function and Control
Interrupt trigger
Writing “1” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
= 1) generates an interrupt request.
Writing “0” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
= 1) clears the interrupt request.
Interrupt control
No enable/disable register is provided for this interrupt.
Interrupt flag
Set in bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0) .
EI2OS support
Not supported by the extended intelligent I/O service (EI2OS) .
R0
Internal data bus
Delayed interrupt request generation/
clear register (DIRR)
S
R
Interrupt
request signal
Interrupt request
latch
: Undefined
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