參數(shù)資料
型號: MB90F548GLSPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 30/72頁
文件大?。?/td> 1798K
代理商: MB90F548GLSPMC
MB90540G/545G Series
36
DS07-13703-7E
(Continued)
*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
Notes :
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first
event. So it is recommended not to use the EI2OS for this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should
be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other
interrupt should be disabled.
相關(guān)PDF資料
PDF描述
MB90548GSPMC 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
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