參數(shù)資料
型號(hào)： MB90F523PFV-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁數(shù)： 86/127頁
文件大?。?/td> 2636K
代理商： MB90F523PFV-G
61
MB90520 Series
10. DTP/External Interrupt Circuit
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing.
As request levels, two types of “H” and “L” can be selected for the intelligent I/O service. Rising and falling edges
as well as “H” and “L” can be selected for an external interrupt request.
* : The external peripheral circuit is connected outside the MB90520 series device.
(1) Register Configuration
DTP/interrupt factor register (EIRR)
Address
000031H
bit 7
bit 0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
..... .......
(ENIR)
Initial value
XXXXXXXX B
R/W
Address
000030H
bit 15
bit 8
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
(EIRR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
..... .......
R/W
Initial value
00 000 00 0 B
Address
Low order address 000032H
bit 15
bit 8
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(ELVR upper)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
..... .......
R/W
Initial value
00 000 00 0 B
DTP/interrupt enable register (ENIR)
R/W : Readable and writable
X : Indeterminate
Address
High order address 000033H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(ELVR lower)
Initial value
00 000 00 0 B
R/W
Request level setting register (ELVR)
bit 7
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
..... .......
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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