參數(shù)資料
型號(hào)： MB90F346EPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 62/92頁
文件大小： 2532K
代理商： MB90F346EPMC
MB90340E Series
DS07-13747-4E
65
(9) LIN-UART0/1/2/3
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA
= 40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Notes :
AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
Parameter
Symbol
Pin
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
Internal shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
5 tCP
ns
SCK
↓ → SOT delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
50
+50
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK0 to SCK3,
SIN0 to SIN3
tCP + 80
ns
SCK
↑ → Valid SIN hold time
tSHIXI
SCK0 to SCK3,
SIN0 to SIN3
0
ns
Serial clock “L” pulse width
tSHSL
SCK0 to SCK3
External shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
3 tCP - tR
ns
Serial clock “H” pulse width
tSLSH
SCK0 to SCK3
tCP + 10
ns
SCK
↓ → SOT delay time
tSLOVE
SCK0 to SCK3,
SOT0 to SOT3
2 tCP + 60
ns
Valid SIN
→ SCK ↑
tIVSHE
SCK0 to SCK3,
SIN0 to SIN3
30
ns
SCK
↑ → Valid SIN hold time
tSHIXE
SCK0, SCK1,
SIN0 to SIN3
tCP + 30
ns
SCK fall time
tF
SCK0 to SCK3
10
ns
SCK rise time
tR
SCK0 to SCK3
10
ns
SCK0 to SCK3
2.4 V
0.8 V
SOT0 to SOT3
0.8 V
2.4 V
0.8 V
tSLOVI
SIN0 to SIN3
VIL
VIH
VIL
VIH
tSCYC
tIVSHI
tSHIXI
Internal Shift Clock Mode
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