參數(shù)資料
型號(hào)： MB90F342APF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 6/84頁(yè)
文件大小： 1130K
代理商： MB90F342APF
MB90340 Series
14
(Continued)
Pin No.
Pin name
Circuit
type
Function
LQFP100*2 QFP100*1
92
94
P15
G
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
AD13
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
SIN4
Serial data input pin for UART4 (EVA devices)
93
95
P16
G
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
AD14
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
SOT4
Serial data output pin for UART4 (EVA devices)
94
96
P17
G
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
AD15
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SCK4
Clock I/O pin for UART4 (EVA devices only)
95 to 98
97 to 100
P20 to P23
G
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
A16 to A19
Output pins for A16 to A19 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
PPG9,PPGB,
PPGD,PPGF
Output pins for PPGs
99 to 2
1 to 4
P24 to P27
G
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
A20 to A23
Output pins for A20 to A23 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A20 to A23).
IN0 to IN3
Data sample input pins for input captures ICU0 to ICU3
35
P30
G
General purpose I/O.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
ALE
Address latch enable output pin. This function is enabled when
the external bus is enabled.
IN4
Data sample input pin for input capture ICU4
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參數(shù)描述
MB90F342ASPF-GS-E1 制造商:FUJITSU 功能描述:
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MB90F342CAPFR-GSE1 制造商:FUJITSU 功能描述:
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MB90F342CASPFR-GSE1 制造商:FUJITSU 功能描述:
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