參數(shù)資料
型號(hào): MB90573PMC1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù): 114/120頁
文件大?。?/td> 2711K
代理商: MB90573PMC1
MB90570A/570C Series
DS07-13701-9E
93
(9) UART0 (SCI), UART1 (SCI) Timing
(AVCC = VCC = 5.0 V
±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes :
These are AC ratings in the CLK synchronous mode.
CL is the load capacitance value connected to pins while testing.
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK4
Internal shift clock
mode
CL = 80 pF
+ 1 TTL for an
output pin
8 tCP*—
ns
SCK
↓ → SOT delay
time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
– 80
80
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
100
ns
SCK
↑ → valid SIN hold
time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Serial clock “H” pulse
width
tSHSL
SCK0 to SCK4
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
4 tCP*—
ns
Serial clock “L” pulse
width
tSLSH
SCK0 to SCK4
4 tCP*—
ns
SCK
↓ → SOT delay
time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
—150
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
60
ns
SCK
↑ → valid SIN hold
time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
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