參數(shù)資料
型號： MB90522PFF-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁數(shù)： 20/127頁
文件大小： 2636K
代理商： MB90522PFF-G
MB90520 Series
116
Table 15
Logic 2 (Long) [6 Instructions]
Table 16
Sign Reverse (Byte, Word) [6 Instructions]
Table 17
Normalize Instruction (Long) [1 Instruction]
*1: Set to 4 when the accumulator is all “0”, otherwise set to 6 + (R0).
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes” and
“Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
Mnemonic
#
~
RG
B
Operation
LH AH
IS
T
N
Z
V
C RMW
ANDL
A, ear
ANDL
A, eam
ORL
A, ear
ORL
A, eam
XORL
A, ear
XORL
A, eam
2
2 +
2
2 +
2
2 +
6
7 + (a)
6
7 + (a)
6
7 + (a)
2
0
2
0
2
0
(d)
0
(d)
0
(d)
long (A)
← (A) and (ear)
long (A)
← (A) and (eam)
long (A)
← (A) or (ear)
long (A)
← (A) or (eam)
long (A)
← (A) xor (ear)
long (A)
← (A) xor (eam)
–
*
R
–
Mnemonic
#
~
RG
B
Operation
LH AH
IS
T
N
Z
V
C RMW
NEG
A
NEG
ear
NEG
eam
1
2
2 +
2
3
5 + (a)
0
2
0
2
× (b)
byte (A)
← 0 – (A)
byte (ear)
← 0 – (ear)
byte (eam)
← 0 – (eam)
X
–
*
–
*
NEGW A
NEGW ear
NEGW eam
1
2
2 +
2
3
5 + (a)
0
2
0
2
× (c)
word (A)
← 0 – (A)
word (ear)
← 0 – (ear)
word (eam)
← 0 – (eam)
–
*
–
*
Mnemonic
#
~
RG
B
Operation
LH AH
IS
T
N
Z
V
C RMW
NRML
A, R0
2
*1
1
0
long (A)
← Shift to where “1”
is originally located
byte (R0)
← Number of shifts
in the operation
––––
––
*
–
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相關代理商/技術參數(shù)
參數(shù)描述
MB90522PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller
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