參數(shù)資料
型號: MB90487BPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 8/124頁
文件大?。?/td> 3283K
代理商: MB90487BPMC
MB90480B/485B Series
DS07-13722-11E
105
(13) I2C Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock Timing”.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “
Note of SDA and SCL set-up time”.
Note : VCC
= VCC3 = VCC5
Parameter
Symbol
Condition
Standard-mode
Unit
Min
Max
SCL clock frequency
fSCL
When power supply voltage of
external pull-up resistance is 5.5 V
R
= 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R
= 1.6 kΩ, C = 50 pF*2
0
100
kHz
Hold time (repeated) START condition
SDA
↓ → SCL↓
tHDSTA
4.0
μs
“L” width of the SCL clock
tLOW
4.7
μs
“H” width of the SCL clock
tHIGH
4.0
μs
Set-up time (repeated) START
condition SCL
↑ → SDA↓
tSUSTA
4.7
μs
Data hold time
SCL
↓ → SDA↓↑
tHDDAT
0
3.45*3
μs
Data set-up time
SDA
↓↑ → SCL↑
tSUDAT
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1
≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
fCP*1
≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2
250*4
ns
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1
> 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
fCP*1
> 20 MHz, R = 1.6 kΩ, C = 50 pF*2
200*4
ns
Set-up time for STOP condition
SCL
↑ → SDA↑
tSUSTO
When power supply voltage of
external pull-up resistance is 5.5 V
R
= 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R
= 1.6 kΩ, C = 50 pF*2
4.0
μs
Bus free time between a STOP and
START condition
tBUS
4.7
μs
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