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參數(shù)資料
| 型號： | MB89PV950CF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封裝： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件頁數(shù)： | 22/110頁 |
| 文件大?。?/td> | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 4
(1) I/O area
This area is where various peripherals such as control and data registers
are located. The memory map for the I/O area is given in APPENDIX A.
(2) RAM area
This area is where the static RAM is located. Addresses from 0100
H to
017FH (0100H to 013FH in MB89951, 0100H to 01FF0H in MB89P955 and
MB89PV950) are also used as the general-purpose register area. One can
access these registers through register-related instructions or just treat
them as ordinary RAM.
(3) ROM area
This area is where the internal ROM is located. Addresses from FFC0
H to
FFFFH are also used for the table of interrupt, reset and vector-call
instructions. Table 2–1 shows the correspondence between each interrupt
number or reset and the table addresses to be referenced for the MB89950
series of microcontrollers.
Table 2–1 Table of Reset and Interrupt Vectors
CPU
Table address
Upper data
Lower data
CALLV #0
FFC0H
FFC1H
CALLV #1
FFC2H
FFC3H
CALLV #2
FFC4H
FFC5H
CALLV #3
FFC6H
FFC7H
CALLV #4
FFC8H
FFC9H
CALLV #5
FFCAH
FFCBH
CALLV #6
FFCCH
FFCDH
CALLV #7
FFCEH
FFCFH
Table address
Upper data
Lower data
Interrupt #B
FFE4H
FFE5H
Interrupt #A
FFE6H
FFE7H
Interrupt #9
FFE8H
FFE9H
Interrupt #8
FFEAH
FFEBH
Interrupt #7
FFECH
FFEDH
Interrupt #6
FFEEH
FFEFH
Interrupt #5
FFF0H
FFF1H
Interrupt #4
FFF2H
FFF3H
Interrupt #3
FFF4H
FFF5H
Interrupt #2
FFF6H
FFF7H
Interrupt #1
FFF8H
FFF9H
Interrupt #0
FFFAH
FFFBH
Reset mode
-----
FFFDH
Reset vector
FFFEH
FFFFH
Note: FFFCH is already reserved. When using
FFFDH in the reset mode, write 00H.
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