參數(shù)資料
型號: MB89P485P-SH-102
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PDIP64
封裝: SHRINK, PLASTIC, DIP-64
文件頁數(shù): 11/51頁
文件大?。?/td> 1061K
代理商: MB89P485P-SH-102
19
MB89480/480L Series
I Block Diagram
Main clock
Clock controller
Sub-clock
RAM (512 bytes / 1K bytes)
F2MC-8L
CPU
ROM (16K bytes / 32K bytes)
Other pins
Vcc, Vss, MODE, C *2
In
te
rnal
dat
a
b
u
s
21-bit timebase
UART/SIO
Port
0
Por
t1
X0
X1
P07/INT27/BUZ
P21/SCK
P22/SO
P23/SI
timer
X0A
X1A
Port
3
N-ch open-drain output port
2
Buzzer output
4
LCD controller/driver
32 × 4-bit display
RAM (16 bytes)
8-bit PWM timer
P
o
rt
4
a
nd
P
o
rt
5
*
4
N-ch open-drain I/O port
P10/SEG23/INT10
to
P13/SEG26/INT13
SEG1 t0 SEG7
7
COM0 to COM1
2
V3
V0/SEG0 *3
8
P30/COM2
P31/COM3
Reset circuit
(Watchdog timer)
RST
External interrupt 2
(egde)
4
16
P56/SEG22
to P54/SEG20
oscillator
Watch prescaler
8/16-bit
timer/counter 21,22
CMOS I/O port *4
Po
rt
2
*
4
8/16-bit
timer/counter 11,12
Booster
2
P20/PWM
P24/C1/TO2 *1
P25/C0/EC2 *1
P26/V1/TO1
P27/V2/EC1
CMOS I/O port
External interrupt 2
(level)
8
8-bit
P05/INT25/PWC
PWC timer
6-bit PPG
P06/INT26/PPG
P04/INT24 *1
P02/INT22
P03/INT23 *1
to P00/INT20
10-bit
A/D converter
P14/SEG27/AN0 *1
to
P17/SEG30/AN3 *1
AVcc
AVss
4
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.
Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled.
*2: For product other than MB89P485, C pin is NC pin.
*3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0.
*4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port.
N-ch open-drain I/O port
P57
3
P53/SEG19
to P50/SEG16
4
P47/SEG15
to P44/SEG12
4
P43/SEG11
to P40/SEG8
4
相關(guān)PDF資料
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