參數(shù)資料
型號(hào): MB89F538-201PV
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PBCC64
封裝: PLASTIC, BCC-64
文件頁(yè)數(shù): 39/64頁(yè)
文件大?。?/td> 832K
代理商: MB89F538-201PV
MB89530 Series
44
(7) I2C Timing
(VCC
= 3.0 V, AVss = Vss = 0 V, TA = 40 °C to +85 °C)
Notes :
For tinst see “ (4) Instruction Cycle”.
The value “m” in the above table is the value from the shift clock frequency setting bits (CS4-CS3) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2-CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
tDOSU appears when the interrupt period is longer than the SCL “L” width.
The rated values for SDA and SCL assume a start up time of 0 ns.
Parameter
Symbol
Pin
name
Condition
Value
Unit
Remarks
Min
Max
Start condition output
tSTA
SCL
SDA
1
/ 4 tinst ×
m
× n 20
1
/ 4 tinst ×
m
× n + 20
ns
Master only
Stop condition output
tSTO
SCL
SDA
1
/ 4 tinst ×
(m
× n + 8) 20
1
/ 4 tinst ×
(m
× n + 8) + 20
ns
Master only
Start condition detection
tSTA
SCL
SDA
1
/ 4 tinst × 6 + 40
ns
Stop condition detection
tSTO
SCL
SDA
1
/ 4 tinst × 6 + 40
ns
Restart condition output
tSTASU
SCL
SDA
1
/ 4 tinst ×
(m
× n + 8) 20
1
/ 4 tinst ×
(m
× n + 8) + 20
ns
Master only
Restart condition detection
tSTASU
SCL
SDA
1
/ 4 tinst × 4 + 40
ns
SCL output “L” width
tLOW
SCL
1
/ 4 tinst ×
m
× n 20
1
/ 4 tinst ×
m
× n + 20
ns
Master only
SCL output “H” width
tHIGH
SCL
1
/ 4 tinst ×
(m
× n + 8) 20
1
/ 4 tinst ×
(m
× n + 8) + 20
ns
Master only
SDA output delay time
tDO
SDA
1
/ 4 tinst × 4 20 1 / 4 tinst × 4 + 20 ns
Setup after SDA output
interrupt interval
tDOSU
SDA
1
/ 4 tinst × 4 20
ns
SCL input “L” width
tLOW
SCL
1
/ 4 tinst × 6 + 40
ns
SCL input “H” width
tHIGH
SCL
1
/ 4 tinst × 2 + 40
ns
SDA input setup
tSU
SDA
40
ns
SDA input hold
tHO
SDA
0
ns
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