參數(shù)資料
型號(hào)： MB89635RPF
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁數(shù)： 134/153頁
文件大?。?/td> 7326K
代理商： MB89635RPF
MB89630 SERIES HARDWARE MANUAL
2-58
(4) Description of functions
(a) Operation modes
The operation modes of the 16-bit timer/counter can be selected from the timer and counter modes by a
combination of bit 3 (TCS0) and bit 4 (TCS1) of the TMCR.
(1) Timer mode
Setting values other than 00
B at bit 3 (TCS0) and bit 4 (TCS1) of the TMCR gives the timer mode.
The TCR increments according to the internal clock source (1/4 oscillation or instruction cycle); exter-
nal-count input is disabled at this time. Detecting an overflow enables generation of time intervals up
to 216 times the clock source (65536 instruction cycles). The maximum time intervals are 32.8 ms at 8
MHz oscillation.
(2) Counter mode
Setting values other than 00
B at bit 3 (TCS0) and bit 4 (TCS1) of the TMCR gives the counter mode.
The edge polarities given in Table 2-1 can be selected according to the value to be set. The counter
mode is divided into three according to the setting of the edge detection for the external-count input.
In the counter mode, the TCR increments each time the arbitrary edge of the EC input for the exter-
nal-count clock pin is detected. (The internal clock source is disabled at this time.) This enables
counting with the number of external-count input events (arbitrary edges). The pulse width of the
external-count clock input can be input from
8 to a minimum width of two instruction cycles (This cor-
responds to DC to 1/2 instruction cycle).
(b) Count start/stop
The TCR starts counting when 1 is written at bit 0 (TCS) of the TMCR, and stops counting when 0 is writ-
ten.
(c) Counting and interrupt occurrence
In the timer mode, the TCR is incremented every one instruction cycle of the clock source; in the counter
mode, it is incremented each time the effective edge of the external-count input is detected. When the
counter value changes from FFFF
H to 0000H (overflows), an overflow-interrupt request is output to the CPU
if the interrupt flag TCEF (bit 2) of the TMCR is set to 1 and the interrupt-request output-enable bit TCIE (bit
1) is 1.
Any byte value can be set at the TCR. (This setting should be done when the counter stops (TCS = 0).)
The value of the TCR can be read even during operation. To read, always use the word-transfer instruc-
tions (MOVW A, dir, etc.).
(d) Counter clear
The TCR is cleared to 0000
H when 0 is written at bit 5 (TCR) of the TMCR. If clearing is performed concur
rently with overflow, the interrupt flag is not set.
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