參數(shù)資料
型號: MB89567APMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 39/64頁
文件大小: 1640K
代理商: MB89567APMC
MB89560A Series
44
DS07-12555-3E
(7) I2C timing
(Vcc = 5.0 V, AVSS = VSS = 0.0 V, TA = –40
°C to +85 °C)
*1 : For information in tinst, see “ (4) Instruction Cycle”.
*2 : M is defined in the ICCR CS4 and CS3 (bit 4, bit 3) . For details, please refer to the H/W manual register
explanation.
*3 : N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) .
*4 : When the interrupt period is greater than SCL “L” width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Max
Start condition output
tSTA
SCL
SDA
1/4 tinst*1
×
M*2 x N*3 - 20
1/4 tinst
×
M*2 x N*3 + 20
ns
Master
mode
Stop condition output
tSTO
SCL
SDA
1/4 tinst
×
(M*2
× N*3 + 8) - 20
1/4 tinst
×
(M*2
× N*3 + 8) + 20
ns
Master
mode
Start condition detect
tSTA
SCL
SDA
1/4 tinst
× 6 + 40
ns
Stop condition detect
tSTO
SCL
SDA
1/4 tinst
× 6 + 40
ns
Re-start condition
output
tSTASU
SCL
SDA
1/4 tinst
×
(M*2
× N*3 + 8) - 20
1/4 tinst
×
(M*2
× N*3 + 8) + 20
ns
Master
mode
Re-start condition
detect
tSTASU
SCL
SDA
1/4 tinst
× 4 + 40
ns
SCL output LOW
width
tLOW
SCL
1/4 tinst
×
M*2
× N*3 - 20
1/4 tinst
×
M*2
× N*3 + 20
ns
Master
mode
SCL output HIGH
width
tHIGH
SCL
1/4 tinst
×
(M*2
× N*3 + 8) - 20
1/4 tinst
×
(M*2
× N*3 + 8) + 20
ns
Master
mode
SDA output delay
tDO
SDA
1/4 tinst
× 4 - 20
1/4 tinst
× 4 + 20
ns
SDA output setup
time after interrupt
tDOSU
SDA
1/4 tinst
× 4 - 20
ns
*4
SCL input LOW
pulse width
tLOW
SCL
1/4 tinst
× 6 + 40
ns
SCL input HIGH
pulse width
tHIGH
SCL
1/4 tinst
× 2 + 40
ns
SDA input setup time
tSU
SDA
40
ns
SDA hold time
tHO
SDA
0
ns
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