參數(shù)資料
型號(hào): MB89538HPF
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP64
封裝: PLASTIC, QFP-64
文件頁(yè)數(shù): 23/50頁(yè)
文件大?。?/td> 1151K
代理商: MB89538HPF
3
MB89530H Series
s PRODUCT LINEUP
MB89537H
MB89537HC
MB89538H
MB89538HC
MB89P538
MB89PV530
Classification
Mass production products
(mask ROM product)
OTP
Piggy-back
ROM size
32 K x 8 bits
48 K
× 8 bits
RAM size
1K x 8 bits
2K
× 8 bits
CPU functions
Number of instructions:
: 136
Instruction bit length:
: 8 bits
Instruction length:
: 1 to 3 bytes
Data bit length:
: 1, 8, 16 bits
Minimum execution time:
: 0.32
s/12.5 MHz
Minimum interrupt processing time:
: 2.88
s/12.5 MHz
Ports
Input port
: 5 pins
Output-only ports (CMOS)
: 8 pins
I/O ports (N-channel open drain)
: 2 pins
I/O ports (CMOS)
: 38 pins
Total
: 53 pins
Clock
Dual/Single
Wild Register
Yes
PWM Timer
8 bits reload timer operation(toggled output capable, operating clock cycle: 1, 8, 16, 64 tinst).
8 bits resolution PWM operation( conversion cycle:256 tinst to 256 X 64 tinst)
2 channels or combine to 1 channel with channel 1 being the count clock of channel 2.
Pulse width count timer
8 bits timer operation (underflow output capable, operating clock cycle:1, 4, 32 tinst, external)
8 bits reload timer (toggled output capable, operating clock cycle: 1, 4, 32 tinst, external)
8 bits pulse-width measurement
6-bit PPG
Internal 6-bit counter
Output frequency: pulse width and cycle are program selectable
12-bit PPG
2 channels, Internal 12-bit counter
Output frequency: pulse width and cycle are program selectable
I2C interface
MB89537H/MB89538H do not have I2C interface.
1 channel, Use a 2-wire protocol to communicate with other device
16-bit Timer/Counter
16-bit timer operation (operating clock period: 1 tinst, external)
16-bit event counter operation (rising, falling, or both edges can be selected)
16 bits x 1 channel
Serial I/O
8-bit length; Selectable LSB-first or MSB-first; 4 shift clock mode selectable
UART/SIO
Transfer data length: 7, 8 bits for UART, 8 bits for SIO
support sub-clock mode
UART
CLK-synchronous/CLK-asynchronous data transfer capable
(4,6,7 and 8 bits with parity bit ; 5,7,8 and 9 bits without parity bit)
External interrupt 1
Edge detection of 4 external sources; Interrupt can be generated at the same time flag is set; Can
be used to release the sleep or stop mode.
External interrupt 2
8 external interrupt input (level interrupt); Available for the wake up interrupt input.
A/D converter
10-bit resolution
× 8 channels ( conversion time: 60 tinst )
A/D conversion function Supports repeated activation by an external or internal clock.
Reference voltage input provided (AVR).
Standby mode
Sleep mode, stop mode and clock mode
Process
CMOS
Operating Voltage
3.5V ~ 5.5V
2.2V ~ 5.5 V
Note : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main
clock, or 1/2 of the subclock if subclock mode is selected.
Part number
Parameter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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