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參數資料
| 型號： | MB881822AWQN-G-JN-EFE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PQCC24 |
| 封裝： | 2.50 X 3.50 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, PLASTIC, QFN-24 |
| 文件頁數： | 16/32頁 |
| 文件大小： | 938K |
| 代理商： | MB881822AWQN-G-JN-EFE1 |
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MB88182
DS04-29138-5E
23
(Ta
= 40 °C to + 85 °C, VDDE = 1.8 V ± 0.15 V, VDP = 1.8 V ± 0.15 V)
*1 : Part number: MB881822A/MB881822B
*2 : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.
Parameter
Symbol
Pin
Conditions
Value
Unit
Min
Typ
Max
Output
frequency
fOUT
CLK1*1,
CLK2,
CLK3,
CLK4
Load capacitance
10 pF or less
8
50
MHz
Load capacitance
15 pF or less
8
40
Output slewing
rate
SR
CLK1*1,
CLK2,
CLK3,
CLK4
Slewing rate low,
Driving ability small setting
15 pF load capacitance
8 MHz to 25 MHz
0.13
V/ns
Slewing rate high,
Driving ability small setting
15 pF load capacitance
8 MHz to 30 MHz
0.14
Slewing rate low,
Driving ability large setting
15 pF load capacitance
8 MHz to 30 MHz
0.19
Slewing rate high,
Driving ability large setting
15 pF load capacitance
8 MHz to 40 MHz
0.22
Slewing rate high,
Driving ability large setting
10 pF load capacitance
8 MHz to 50 MHz
0.29
CKREF
15 pF load capacitance
0.14
Output
impedance
ZO
CLK1*1,
CLK2,
CLK3,
CLK4
Driving ability small setting
80
Ω
Driving ability large setting
40
CKREF
80
Output clock
duty cycle
tDCC
CLK1*1,
CLK2,
CLK3,
CLK4
VDDE
/ 2,
VDP
/ 2
45
55
%
CKREF
VDP
/ 2tDCI 5*2
tDCI
+ 5*2
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