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參數(shù)資料
| 型號： | MB881821BWQN-G-JNE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PQCC24 |
| 封裝： | 2.50 X 3.50 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 938K |
| 代理商： | MB881821BWQN-G-JNE1 |
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MB88182
10
DS04-29138-4E
■ PIN SETTING
ENS Modulation enable setting
When setting “0” to the ENS pin, the spectrum will not spread.
The setting is for CLK2 (SSCG1) and CLK3, and CLK4 (SSCG2).
XPD Power down setting
The pin in XPDREF, XPD1, XPD2, XPD3 and XPD4 is connected to the pull-up resistor.
However, the pull-up resistor is cut off during “0” input.
When both XPD3 and XPD4 are “0”, SSCG2 is in the power down state.
ENS
Modulation
0
No modulation
1 (2.6 V)
Modulation
XPDREF
0
CKREF is fixed to the output “L”.
1 (2.6 V)
CKREF is the clock output.
XPD1
0
PLL1 is in the power down state.
CLK1 is fixed to the output “L”.
1 (2.6 V)
PLL1 and CLK1 are in operation.
XPD2
0
SSCG1 is in the power down state.
CLK2 is fixed to the output “L”.
1 (2.6 V)
SSCG1 and CLK2 are in operation.
XPD3
0
CLK3 is fixed to the output “L”.
1 (2.6 V)
SSCG2 and CLK3 are in operation.
XPD4
0
CLK4 is fixed to the output “L”.
1 (2.6 V)
SSCG2 and CLK4 are in operation.
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