- 您現(xiàn)在的位置：買賣IC網 > PDF目錄26791 > MB88153APNF-G-101-JNEFE1 (FUJITSU LTD) 88153 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 PDF資料下載
參數(shù)資料
| 型號： | MB88153APNF-G-101-JNEFE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 88153 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 3.90 X 5.05 MM, 1.27 MM PITCH, 1.75 MM HEIGHT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 230K |
| 代理商： | MB88153APNF-G-101-JNEFE1 |
MB88153A
5
■ HANDLING DEVICES
Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an
input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up,
if it occurs, significantly increases the power supply current and may cause thermal destruction of an element.
When you use this device, be very careful not to exceed the maximum rating.
Handling unused pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.
Unused output pin should be opened.
Power supply pins
Please design connecting the power supply pin of this device by as low impedance as possible from the current
supply source.
We recommend connecting electrolytic capacitor (about 10
F) and the ceramic capacitor (about 0.01 F) in
parallel between VSS pin and VDD pin near the device, as a bypass capacitor.
Clock I/O circuit
Noise near the CKIN pin may cause the device to malfunction. Design the printed circuit board so that the wiring
for the clock input does not intersect any other wiring.
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of CKIN pin.
Design the printed circuit board that surrounds the CKIN and CKOUT pins with ground.
相關PDF資料 |
PDF描述 |
|---|---|
| MC100E104FNR2 | 100E SERIES, 5 2-INPUT AND/NAND GATE, PQCC28 |
| MC100E131FNR2 | 100E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28 |
| MC100E156FNR2 | 100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28 |
| MC100E158FNR2 | 100E SERIES, 5 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PQCC28 |
| MC100E167FN | 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB88153APNF-G-101-JNERE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Spread Spectrum Clock Generator |
| MB88153APNF-G-110-JNE1 | 功能描述:IC SSCG 134MHZ 3.3V 8SOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| MB88153APNF-G-110-JNEFE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Spread Spectrum Clock Generator |
| MB88153APNF-G-110-JNERE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Spread Spectrum Clock Generator |
| MB88153APNF-G-111-JNE1 | 功能描述:IC SSCG 134MHZ 3.3V 8SOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
發(fā)布緊急采購，3分鐘左右您將得到回復。