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參數(shù)資料
| 型號： | MB86612PBT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMM CONTROLLER, PBGA120 |
| 封裝： | PLASTIC, FBGA-120 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 574K |
| 代理商： | MB86612PBT |
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MB86612
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (MPEG, DVC) protocols.
Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh).
Address
Write operation
Read operation
HEX
A5A4A3A2
A1
10
01000
Sending time stamp offset
setting register
Receiving time stamp
display register (high)
12
01001
Sending time stamp offset
setting register
Receiving time stamp
display register (low)
14
01010
Sending CIP header
setting register (highest)
Receiving CIP header
display register (highest)
16
01011
Sending CIP header
setting register (high)
Receiving CIP header
display register (high)
18
01100
Sending CIP header
setting register (low)
Receiving CIP header
display register (low)
1A
01101
Sending CIP header
setting register (lowest)
Receiving CIP header
display register (lowest)
1C
01110
OMPR (high)
←
1E
01111
OMPR (low)
←
20
10000
OPCR0 (high)
←
22
10001
OPCR0 (low)
←
24
1
0
1
0
(reserved)
←
26
1
0
1
(reserved)
←
28
1
0
1
0
(reserved)
←
2A
1
0
1
0
1
(reserved)
←
2C
10110
IMPR (high)
←
2E
10111
IMPR (low)
←
30
11000
IPCR0 (high)
←
32
11001
IPCR0 (low)
←
34
1
0
1
0
(reserved)
←
36
1
0
1
(reserved)
←
38
1
0
(reserved)
←
3A
1
0
1
(reserved)
←
3C
1
0
AV mode setting register
AV status register
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86612PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86613 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613S | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394 Open HCI Controller |
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