
FUJISTU LIMITED PRELIMINARY AND CONFIDENTIAL
MB86295S <Coral-LP>
149
Specification Manual Rev1.1
10.2.1 Host interface registers
MRO (Mirror Register Override)
Register
address
HostBaseAddress + 001CH
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
4 3 2 1 0
Bit field name
Reserved
MRO
R/W
R0
RW
Initial value
0
Writing a “1b” to this register overrides use of the Geometry/Draw Engine Mirror registers which reside
in the host interface. Access to the Mirror registers is faster than the source registers in the
Geometry/Draw Engines. For normal operation this register need not be used and should be kept as
“0b”.
IST (Interrupt STatus)
Register
address
HostBaseAddress + 20H
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
4 3 2 1 0
Bit field name
IST
*1 IST
Reserved
Resv
Reserved
IST
R/W
RW0
R
RW0 R0
RW0
R0
R0W0
R0
RW0
Initial value
0
0 0
0
*1 Reserved
This register indicates the current interrupt status. It shows that an interrupt request is issued when
“1” is set to this register. The interrupt status is cleared by writing “0” to this register.
Bit 0
CERR (Command Error Flag)
Indicates drawing command execution error interrupt
Bit 1
CEND (Command END)
Indicates drawing command end interrupt
Bit 2
VSYNC (Vertical Sync.)
Indicates vertical interrupt synchronization
Bit 3
FSYNC (Frame Sync.)
Indicates frame synchronization interrupt
Bit 4
SYNCERR (Sync. Error)
Indicates external synchronization error interrupt
Bit 17 and 16
Reserved
This field is provided for testing.
Normally, the read value is “0”, but note that it may be “1” when a drawing command
error (Bit 0) has occurred.
Bit 24
TIM (Timeout)
Indicates that an internal FIFO or Bus timeout has occurred. The TCS (Timeout
Control/Status) register may be read to determine the cause o f the timeout.
Bit 26
SII (Serial Interface Interrupt)
Indicates a serial interface write/read has completed.
Bit 27
GI (GPIO Interrupt)
Indicates that a GPIO input has changed state (0->1 or 1->0)