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參數(shù)資料
| 型號(hào)： | MB8502S072AC-100 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2M×74Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×74位 同步動(dòng)態(tài)RAM) |
| 中文描述： | 200萬× 74Bit的CMOS同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器（SDRAM）的CMOS（200萬× 74位同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 328K |
| 代理商： | MB8502S072AC-100 |
DS05-11112-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
Buffered
2 M
×
SYNCHRONOUS DYNAMIC RAM DIMM
MB8502S072AC-100/-84/-67
72 BIT
200-pin, 1-bank, based on 2 M
×
8 BIT SDRAMs with PLL
I
DESCRIPTION
The Fujitsu MB8502S072AC is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM)
module consisting of nine MB81117822A devices which organized as two banks of 1 M
possible to minimize the skews of input signals such as clock and address signal by the PLL clock driver and
register buffers mounted. The MB8502S072AC is optimized for those applications requiring high speed, high
performance and large memory storage, and high density memory organizations.
This module is ideally suited for supercomputers, workstations, high-end PCs, laser printers, high resolution
graphic adapters, accelerators, and other applications where a simple interface is needed.
×
8 bits. This module is
I
PRODUCT LINE & FEATURES
Parameter
MB8502S072AC-100
MB8502S072AC-84
MB8502S072AC-67
Clock Frequency
100 MHz max.
84 MHz max.
67 MHz max.
Burst Mode Cycle Time
10 ns max. (CL = 4)
15 ns max. (CL = 3)
12 ns max. (CL = 4)
17 ns max. (CL = 3)
15 ns max. (CL = 4)
20 ns max. (CL = 3)
RAS Access Time
54.5 ns max.
56.5 ns max.
60.5 ns max.
CAS Access Time
24.5 ns max.
26.5 ns max.
30.5 ns max.
Output Valid from Clock
9 ns max. (CL = 4)
9.5 ns max. (CL = 3)
9 ns max. (CL = 4)
9.5 ns max. (CL = 3)
9.5 ns max. (CL = 4)
10.5 ns max. (CL = 3)
Power
Dissipation
Burst Mode
5281 mW max.
4810 mW max.
4342 mW max.
Power Down Mode
493 mW max.
428 mW max.
367 mW max.
Buffered 200-pin DIMM Socket Type
(Lead pitch: 1.27 mm)
Conformed to JEDEC Standard
Organization: 2,097,152 words
×
72 bits (ECC)
Memory: MB81117822A (2 M
×
8, 2-bank)
×
9 pcs.
3.3 V
±
0.3 V Supply Voltage
All input/output LVTTL compatible
2048 Refresh Cycle every 32.8 ms
Auto and Self Refresh
CKE Power Down Mode
Output Enable and Input Data Mask
PLL Clock Driver/Register Buffer/Input Buffer
Module size:
1.50” (height)
×
6.05” (length)
×
0.11” (thick)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB8502S072AC-67 | CMOS 2M×74Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×74位 同步動(dòng)態(tài)RAM) |
| MB8502S072AC-84 | CMOS 2M×74Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×74位 同步動(dòng)態(tài)RAM) |
| MB8504D064AA-60 | CMOS 4M×64 BIT Hyper Page Mode DRAM Module(CMOS 4M×64 位超級(jí)頁面存取模式動(dòng)態(tài)RAM模塊) |
| MB8504D064AA-70 | CMOS 4M×64 BIT Hyper Page Mode DRAM Module(CMOS 4M×64 位超級(jí)頁面存取模式動(dòng)態(tài)RAM模塊) |
| MB8504E032AA-70 | 4 M×32 BITS Hyper Page Mode DRAM Module(CMOS 4 M×32 位超級(jí)頁面存取模式動(dòng)態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8508S064CE-100 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM |
| MB85101BAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101BBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
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