參數(shù)資料
型號(hào)： MB81F643242C-70
廠商： Fujitsu Limited
英文描述： 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM
中文描述： 4 × 512 kX的32位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 1/56頁(yè)
文件大?。?/td> 1001K
代理商： MB81F643242C-70
AE0.1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ADVANCED INFO.
MEMORY
CMOS
4
×
512 K
×
32 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F643242C-60/-70/-10
CMOS 4-Bank
×
524,288-Word
×
32 Bit
Synchronous Dynamic Random Access Memory
I
DESCRIPTION
The Fujitsu MB81F643242C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F643242C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F643242C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
I
PRODUCT LINE & FEATURES
Parameter
MB81F643242C
-70
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
143 MHz max.
10 ns min.
7 ns min.
6 ns max.
5.5 ns max.
155 mA max.
Reference
Value@ 67 MHz,
CL
=
3
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
67 MHz max.
20 ns min.
15 ns min.
7 ns max.
7 ns max.
100 mA max.
-60
-10
CL - t
RCD
- t
RP
CL = 2
CL = 3
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
167 MHz max.
10 ns min.
6 ns min.
6 ns max.
5.5 ns max.
165 mA max.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
100 MHz max.
15 ns min.
10 ns min.
7 ns max.
7 ns max.
115 mA max.
2 mA max.
2 mA max.
Clock Frequency
Burst Mode Cycle Time
CL = 2
CL = 3
CL = 2
CL = 3
Access Time from Clock
Operating Current
Power Down Mode Current (I
CC2P
)
Self Refresh Current (I
CC6
)
Single +3.3 V Supply ±0.3 V tolerance
LVTTL compatible I/O interface
4 K refresh cycles every 64 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
Programmable burst type, burst length, and
CAS latency
Auto-and Self-refresh (every 15.6
μ
s)
CKE power down mode
Output Enable and Input Data Mask
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