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參數(shù)資料
| 型號(hào)： | MB40D001PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | DAC |
| 英文描述： | D/A Converter for Digital Tuning |
| 中文描述： | SERIAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | MB40D001PFV |
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MB40D001
Note: After power V
CC
D is turned ON (or after a reset), the state of pins and registers is as follows.
ESR settings have priority in determining pin states. Switching between input standby state and analog output
state is enabled even when the ESR value is “1”. When the ESR value returns to “0”, the pin returns to its
previously defined state.
In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output
state.
Pin
State
AO
1
to AO
4
D
11
/AO
5
to D
4
/AO
12
D
3
to D
0
“L” output
Hi-Z state (input state)
Hi-Z state (input state)
Register
State
Shift register
D/A register
Parallel output register
Expander status register (ESR)
Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state).
All reset to “0”.
Not defined (retain prior state).
All reset to “0”.
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