
Maxim Integrated Products 12
MAXQ618
16-Bit Microcontroller with Infrared Module
Memory
The microcontroller incorporates several memory types:
80KBflashmemory
2KBSRAMdatamemory
1.5KButilityROM
Softstack
Stack Memory
The device provides a soft stack that can be used to store
program return addresses (for subroutine calls and inter-
rupt handling) and other general-purpose data. This soft
stack is located in the 2KB SRAM data memory, which
means that the SRAM data memory must be shared
between the soft stack and general-purpose application
data storage. However, the location and size of the soft
stack is determined by the user, providing maximum
flexibility when allocating resources for a particular appli-
cation. The stack is used automatically by the processor
when the CALL, RET, and RETI instructions are executed
and when an interrupt is serviced. An application can
also store and retrieve values explicitly using the stack by
means of the PUSH, POP, and POPI instructions.
The SP pointer indicates the current top of the stack,
which initializes by default to the top of the SRAM data
memory. As values are pushed onto the stack, the SP
pointer decrements, which means that the stack grows
downward towards the bottom (lowest address) of the
data memory. Popping values off the stack causes the
SP pointer value to increase. Refer to the MAXQ610
User’s Guide for more details.
Utility ROM
The utility ROM is a 1.5KB block of internal ROM memory
located in program space beginning at address 8000h.
This ROM includes the following routines:
Productiontestroutines(internalmemorytests,mem-
ory loader, etc.), which are used for internal testing
only, and are generally of no use to the end-applica-
tion developer
User-callable routines for buffer copying and fast
table lookup (more information on these routines can
be found in the MAXQ610 User’s Guide)
Following any reset, execution begins in the utility ROM
at address 8000h. At this point, unless test mode has
been invoked (which requires special programming
through the JTAG interface), the utility ROM in the device
always automatically jumps to location 0000h, which is
the beginning of user application code.
Watchdog Timer
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the appli-
cation software. If software is operating correctly, the
counter is periodically reset and never reaches its maxi-
mum count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
215 to 224 system clock cycles. An interrupt is gener-
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires. See
Table 1.
Table 1. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0]
WATCHDOG CLOCK
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (s)
00
Sysclk/215
2.7ms
42.7
01
Sysclk/218
21.9ms
42.7
10
Sysclk/221
174.7ms
42.7
11
Sysclk/224
1.4s
42.7