Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs in Ultra-Tiny 1.9mm " />
參數(shù)資料
型號： MAXADCLITE+
廠商： Maxim Integrated Products
文件頁數(shù)： 17/22頁
文件大?。?/td> 0K
描述： KIT EVALUATION FOR MAX11645
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 94.4k
數(shù)據(jù)接口： USB
輸入范圍： ±VREF/2
工作溫度： -40°C ~ 85°C
已用 IC / 零件： MAX11645
已供物品： 板，軟件
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644),
fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
μs
Hold Time for START Condition
tHD,STA
0.6
μs
Low Period of the SCL Clock
tLOW
1.3
μs
High Period of the SCL Clock
tHIGH
0.6
μs
Setup Time for a Repeated START
(Sr) Condition
tSU,STA
0.6
μs
Data Hold Time
tHD,DAT
(Note 11)
0
900
ns
Data Setup Time
tSU,DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Measured from 0.3VDD - 0.7VDD
20 + 0.1CB
300
ns
Fall Time of SDA Transmitting
tF
Measured from 0.3VDD - 0.7VDD (Note 12)
20 + 0.1CB
300
ns
Setup Time for STOP Condition
tSU,STO
0.6
μs
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)
Serial-Clock Frequency
fSCLH
(Note 14)
1.7
MHz
Hold Time, Repeated START
Condition
tHD,STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated START
Condition
tSU,STA
160
ns
Data Hold Time
tHD,DAT
(Note 11)
0
150
ns
Data Setup Time
tSU,DAT
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
20
80
ns
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