參數(shù)資料
型號: MAX9949DCCB+TD
廠商: Maxim Integrated Products
文件頁數(shù): 7/23頁
文件大?。?/td> 0K
描述: IC PMU DUAL 64TQFP
標(biāo)準(zhǔn)包裝: 750
系列: *
PMU Control
Programming both PMUs with the same data requires a
16-bit word. Programming each PMU with separate
data requires two 16-bit words.
The address bits specify which input registers the shift
register loads. Table 2 describes the function of the
address bits.
Bits (C2, C1) specify how the data loads into the second
rank PMU registers. These two control bits serve a similar
function as the
LOAD input. The specified actions occur
when
CS goes high, whereas the LOAD input loads the
PMU register anytime. When either C2 or C1 is low, the
corresponding PMU register is transparent. Table 3
describes the function of the two control bits.
The NOP operation requires A1 = A2 = C1 = C2 = 0. In
this case, the data transfers through the shift register
without changing the state of the MAX9949/MAX9950.
C1 = C2 = 0 allows for data transfer from the shift register
to the input register without transferring data to the PMU
register (unless the
LOAD input is low). This permits the
latching of data into the PMU register at a later time by
the
LOAD input or subsequent command.
Table 4 summarizes the possible control and address
bit combinations.
When asynchronously latching only one PMU’s data,
the input register of the other PMU maintains the same
data. Therefore, loading both PMU registers would
update the one PMU with new data while the other PMU
remains in its current state.
Mode Selection
Four bits from the control word select between the vari-
ous modes of operation. INMODE selects between the
two input analog control voltages. FMODE selects
whether the PMU forces a voltage or a current. MMODE
selects whether the DUT current or DUT voltage is
directed to the MSR_ output.
HI-ZFORCE places the
driver amplifier in a high-output impedance state. Table
5 describes the various force and measure modes of
operation.
MAX9949/MAX9950
Dual Per-Pin Parametric Measurement Units
______________________________________________________________________________________
15
BIT
BIT NAME
15
INMODE
14
FMODE
13
MMODE
12
RS2
11
RS1
10
RS0
9CLENABLE
8
HI-ZFORCE
7
HI-ZMSR
6
DISABLE
5
Don’t care
4
Don’t care
3A2
2A1
1C2
0C1
Table 1. Bit Order
A2
A1
OPERATION
0
Do not update any input register (NOP).
0
1
Only update input register A.
1
0
Only update input register B.
11
Update both input registers with the same
data.
Table 2. Address Bit
C2
C1
OPERATION
0
Data stays in input register.
01
Transfer PMU-A input register to PMU
register.
10
Transfer PMU-B input register to PMU
register.
11
Transfer both input registers to the PMU
registers.
Table 3. Control Bit
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