參數(shù)資料
型號(hào): MAX9911EWT+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/17頁
文件大小: 0K
描述: IC OPAMP RRIO 200KHZ SGL 6WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.1 V/µs
增益帶寬積: 200kHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 200µV
電流 - 電源: 4µA
電流 - 輸出 / 通道: 15mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 6-WFBGA,WLPBGA
供應(yīng)商設(shè)備封裝: 6-WLP(1.27x.87)
包裝: 帶卷 (TR)
MAX9910–MAX9913
200kHz, 4A, Rail-to-Rail
I/O Op Amps with Shutdown
10
______________________________________________________________________________________
rejection ratio of 95dB (typ) allows the devices to be
powered directly from a battery, simplifying design and
extending battery life.
Power-Up Settling Time
The MAX9910–MAX9913 typically require 5s after
power-up. Supply settling time depends on the supply
voltage, the value of the bypass capacitor, the output
impedance of the incoming supply, and any lead resis-
tance or inductance between components. Op-amp
settling time depends primarily on the output voltage
and is slew-rate limited. Figure 3 shows the MAX991_ in
a noninverting voltage follower configuration with the
input held at midsupply. The output settles in approxi-
mately 18s for VDD = 3V (see the Typical Operating
Characteristics for power-up settling time).
Shutdown Mode
The MAX9911/MAX9913 feature active-low shutdown
inputs. The MAX9911/MAX9913 enter shutdown in 2s
(typ) and exit in 30s (typ). The amplifiers’ outputs are
in a high-impedance state in shutdown mode. Drive
SHDN low to enter shutdown. Drive SHDN high to
enable the amplifier. The MAX9913 dual-amplifier fea-
tures separate shutdown inputs. Shut down both ampli-
fiers for the lowest quiescent current.
Power-Supply Bypassing and Layout
To minimize noise, bypass VDD with a 0.1F capacitor
to ground, as close to the pin as possible.
Good layout techniques optimize performance
by decreasing the amount of stray capacitance and
inductance to the op amps’ inputs and outputs.
Minimize stray capacitance and inductance by placing
external components close to the IC.
Figure 1. Rail-to-Rail Output Voltage Range
RAIL-TO-RAIL OUTPUT VOLTAGE RANGE
200
s/div
IN_
3V
0V
1V/div
OUT_
1V/div
Figure 2. Using a Resistor to Isolate a Capacitive Load from
the Op Amp
MAX9910–
MAX9913
RISO
CL
RL
AV =
≈ 1V/V
RL
RL + RISO
Figure 3. Power-Up Test Configuration
MAX991_
100k
100k
OUT
IN-
IN+
0V
5.5V
VDD
VSS
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