Dual I2S Stereo Audio Codec 34 ____________" />
參數(shù)資料
型號: MAX9880AETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 28/70頁
文件大?。?/td> 0K
描述: IC CODEC AUDIO STEREO 48TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 立體聲音頻
數(shù)據接口: I²C,I²S,串行,SPI?
ADC / DAC 數(shù)量: 2 / 2
三角積分調變:
動態(tài)范圍,標準 ADC / DAC (db): 82 / 96
電壓 - 電源,模擬: 1.65 V ~ 1.95 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-TQFN-EP(6x6)
包裝: 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
34
______________________________________________________________________________________
BITS
FUNCTION
TDM1/2
TDM Mode Select
1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data.
0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio.
FSW1/2
Frame Sync Width
1 = Frame sync pulse extended to the width of the entire 16-bit first slot 0 data word (TDM1/TDM2 = 1 only;
SLOTDLY[0] must be 0 when FSW is set to 1).
0 = Frame sync pulse is 1 bit wide.
WS2
Word Size
0 = The number of bits per input data word sample is 16 bits, and at least 16 BCLKs per input word are required.
1 = The number of bits per input data word sample is 18 bits, and at least 18 BCLKs per input word transfer is
required. These control bits are only recognized when TDM1/TDM2 are cleared to 0.
Data Loop. Enabling of these bits provides a bridge from one DAI interface to the other. Data format looping could
occur in both directions simultaneously.
BIT
DESCRIPTION
DL1 = 0
Normal operation
DL1 = 1, SEL2 = 1
Enables SDINS1 to SDOUTS2.
DL2 = 0
Normal operation
DL2 = 1, SEL1 = 0
Enables SDINS2 to SDOUTS1.
DL1/2
Note: The LRCLKS1 and LRCLKS2 interfaces must be identical.
Set the SEL1/2, SDOEN1/2, and SDIEN1/2 bits as shown in the table below to connect the S1 and S2 pins to the
DAI1 and DAI2 paths in the MAX9880A.
SETTING
SEL1
SEL2
SDIEN1
SDOEN1
SDIEN2
SDOEN2
Connect S1 pins to DAI1 (DAC and ADC)
0
X
1
0
Connect S2 pins to DAI1 (DAC and ADC)
1
0
1
0
1
Connect S1 pins (DAC only) to DAI2
1
0
1
0
Connect S2 pins (DAC only) to DAI2
X
1
0
1
0
Connect S1 pins (DAC and ADC) to DAI1,
connect S2 to DAI2 (DAC only)
0
1
0
SEL1/SEL2
Connect S2 pins (DAC and ADC) to DAI1,
connect S1 to DAI2 (DAC only)
1
0
1
0
1
SDOEN1/2
SDOUT Enable
1 = Serial-data output enabled on S1/S2 pins.
0 = Serial-data output disabled on S1/S2 pins.
SDIEN1/2
SDIN Enable
1 = Serial-data input to DAI1/2 audio path enabled.
0 = Serial-data input to DAI1/2 audio path disabled.
DMONO1
Mono Playback Mode
0 = Stereo data input on DAI1 path is processed separately.
1 = Stereo data input on DAI1 path is mixed to a single channel and routed to both the left and right DAC.
When operating in mono voice mode (MODE = 1), stereo data may still be input through DAI1 path and optionally
mixed using DMONO1 = 1.
Table 7. Digital Audio Interface Registers (continued)
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