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| 型號： | MAX98089EVKIT#TQFN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/131頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MAX98089-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | DirectDrive® |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | MAX98089 |
| 主要屬性： | 2.8 V ~ 5.5 V 輸入電壓 |
| 已供物品： | 板，線纜，軟件 |
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Low-Power, Stereo Audio Codec
with FlexSound Technology
Table 36. Status and Interrupt Registers
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-drain
output that requires a pullup resistor for proper operation.
Register 0x0F determines which bits in the status register
trigger IRQ to pull low.
REGISTER
BIT
NAME
DESCRIPTION
0x00
(Read Only)
7
CLD
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
6
SLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has com-
pleted slewing from a previous setting to a new programmed setting. If multiple gain
arrays or volume controllers are changed at the same time, the SLD flag is set after the
last volume slew completes. SLD also reports when the digital audio interface soft-start
or soft-stop process has completed. MCLK is required for proper SLD operation.
0 = No volume slewing sequences have completed since the status register was last
read.
1 = Volume slewing complete.
5
ULK
Digital Audio Interface Unlocked
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid clocks.
1
JDET
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first time
power is applied to the IC. Read the status register following such an event to clear JDET
and allow for proper jack detection.
0 = No change in jack configuration.
1 = Jack configuration has changed.
0x0F
7
ICLD
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
6
ISLD
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
5
IULK
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
1
IJDET
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
Maxim Integrated
117
MAX98089
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GBM24DSEF-S13 | CONN EDGECARD 48POS .156 EXTEND |
| GBM24DRTF-S13 | CONN EDGECARD 48POS .156 EXTEND |
| GBM24DRKF-S13 | CONN EDGECARD 48POS .156 EXTEND |
| RSM12DSEN | CONN EDGECARD 24POS .156 EYELET |
| MAX9860EVKIT+ | KIT EVALUATION FOR MAX9860 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX98089EWY+ | 制造商:Maxim Integrated Products 功能描述:STEREO AUDIO CODEC WITH FLEXSOUND TUNING TECHNOLOGY AND BASI - Rail/Tube |
| MAX98089EWY+T | 功能描述:接口—CODEC Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX98090AETL+ | 功能描述:接口—CODEC 5V 130mW Stereo Headphone Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX98090AETL+T | 功能描述:接口—CODEC 5V 130mW Stereo Headphone Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX98090AEWJ+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
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