參數(shù)資料
型號: MAX98088EWY+T
廠商: Maxim Integrated Products
文件頁數(shù): 85/123頁
文件大?。?/td> 0K
描述: IC CODEC AUDIO FLEXSOUND 63WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,I²S,串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 93 / 101
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 93 / 101
電壓 - 電源,模擬: 1.65 V ~ 2 V
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 63-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 63-WLP
包裝: 帶卷 (TR)
Maxim Integrated Products 64
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 2. Power Management Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
0x4D
7
HPLEN
Left Headphone Enable
0 = Disabled
1 = Enabled
6
HPREN
Right Headphone Enable
0 = Disabled
1 = Enabled
5
SPLEN
Left Speaker Enable
0 = Disabled
1 = Enabled
4
SPREN
Right Speaker Enable
0 = Disabled
1 = Enabled
3
RECLEN
Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output
or left line output.
0 = Disabled
1 = Enabled
2
RECREN
Right Line Output Enable. Use this bit to enable the right line output.
0 = Disabled
1 = Enabled
1
DALEN
Left DAC Enable
0 = Disabled
1 = Enabled
0
DAREN
Right DAC Enable
0 = Disabled
1 = Enabled
0x4E
7
BGEN
Bandgap Enable. Must be enabled for proper operation of 2.5V regulator and associ-
ated circuitry.
0 = Disabled
1 = Enabled
6
SPREGEN
2.5V Regulator Enable. SPREGEN enables a 2.5V internal regulator required for
the ADC, speaker and receiver/line out amplifier. The 2.5V regulator is powered by
SPKLVDD.
0 = Disabled
1 = Enabled
5
VCMEN
Common-Mode Voltage Resistor String Enable. VCMEN enables the common mode
voltage for the input and output amplifiers in the codec.
0 = Disabled
1 = Enabled
4
BIASEN
Chip Bias Enable. BIASEN needs to be set for the codec amplifiers to be enabled.
0 = Disabled
1 = Enabled
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