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參數(shù)資料
| 型號(hào)： | MAX9491EUD |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | XO, clock |
| 英文描述： | Factory-Programmable, Single PLL Clock Generator |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO14 |
| 封裝： | 4.40 MM, MO-153AB-1, TSSOP-14 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | MAX9491EUD |
M
Factory Programmable Single PLL
Clock Generator
6
_______________________________________________________________________________________
Detailed Description
The MAX9491 features a programmable fractional-N
PLL, so frequencies between 4MHz to 200MHz can be
generated. The device provides a buffered PLL clock
output. The crystal input frequency can be between
5MHz and 35MHz, and the clock input between 5MHz
and 50MHz. The internal VCXO has a fine-tuning range
of ±200ppm.
Power-Down
Driving
PD
low places the MAX9491 in power-down
mode.
PD
then sets CLK_OUT to high impedance and
shuts down the PLL. CLK_OUT has an 80k
(typ) inter-
nal pulldown resistor.
Voltage-Controlled Crystal Oscillator
(VCXO)
The MAX9491’s internal VCXO produces a reference
clock for the PLL used to generate the CLK_OUT. The
oscillator uses a crystal as the base frequency refer-
ence and has a voltage-controlled tuning input for micro
adjustment in a ±200ppm range. The tuning voltage,
V
TUNE
, can vary from 0 to 3V as shown in Figure 1. The
crystal should be AT-cut and oscillate on its fundamen-
tal mode with ±30ppm. The crystal shunt capacitor
Pin Description
Typical Operating Circuit/Block Diagram
+3.3V
V
DD
V
DDA
V
DD
V
DD
0.1
μ
F x 3
0.1
μ
F
MAX9491
+3.3V
GND
AGND
TUNE
C1
C2
CLK_OUT
PLL
VCXO
X1
OR REFERENCE
INPUT
X2
OTP
PD
PIN
TQFN
TSSOP
NAME
FUNCTION
1
5
TUNE
VCXO Tune Voltage Input. If using a reference clock input or VCXO is not used,
connect TUNE to V
DD
.
Analog Power Supply. Bypass to GND with a 0.1μF capacitor.
Analog Ground
Ground
Output Clock. Internally pulled down.
Internally Connected. Leave unconnected for normal operation.
Power Supply. Bypass to GND with a 0.1μF capacitor.
Active-Low Power-Down Input. Pull high for normal operation. Drive
PD
low to place
MAX9491 in power-down mode. Internally pulled down.
Crystal Connection 2. Leave unconnected if using a reference clock.
Crystal Connection 1 or Reference Clock Input
Exposed Paddle (TQFN Only). Connect EP to GND or leave unconnected.
2
3
—
—
V
DDA
AGND
GND
CLK_OUT
I.C.
V
DD
4, 10, 11
5
6–9, 14, 19, 20
12, 13, 16
6, 9, 11
7
2, 3, 8, 10
4, 12
15
13
PD
17
18
EP
14
1
—
X2
X1
EP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9491EUD-T | 制造商:Maxim Integrated Products 功能描述:FACTORY-PROGRAMMABLE SINGLE PLL CLO - Tape and Reel |
| MAX9492ETP | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP+ | 功能描述:鎖相環(huán) - PLL Multiple-Output Clock Generator with Spread Spectrum RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP+T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MAX9492ETP-T | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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