參數(shù)資料
型號: MAX9476EUG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: XO, clock
英文描述: Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz
中文描述: 35.328 MHz, OTHER CLOCK GENERATOR, PDSO24
封裝: 4.40 MM, MO-153AD, TSSOP-24
文件頁數(shù): 7/8頁
文件大?。?/td> 177K
代理商: MAX9476EUG
PLL Loop Filter
The PLL contains an integrated VCXO that uses an
external crystal to track the input reference signal and
attenuate input jitter. Figure 1 shows the external loop
filter of the PLL containing resistor R1 and two capaci-
tors, C1 and C2. This loop filter is connected between
LP1 and LP2 as shown in the
Typical Operating Circuit
.
The loop-filter bandwidth is determined by C1, C2, R1,
and R
SET
where R
SET
is used to set the value of the
charge-pump current. The typical values of C1, C2, R1,
and R
SET
are 22nF, 560pF, 1000k
, and 13k
, respec-
tively.
Use the following equation to calculate a PLL loop
bandwidth in Hz:
BW = (R1 x I
SETI
x 1405) / N
where R1 (
) is the resistor in the PLL loop filter (Figure
1), I
SETI
(A) is the charge-pump current calculated from
the equation in the
Charge-Pump Current Setting
section,
and N is the crystal PLL frequency divider equal to 4416.
The loop-damping factor is calculated by:
where C1 (F) and R1 (
) are the values of the capacitor
and the resistor in the PLL loop filter shown in
Figure 1; I
SETI
is calculated as shown in the
Charge-
Pump Current Setting
section and N = 4416.
The following equation shows the relationship between
components C1 and C2 in the loop filter:
C2
C1 / 20
Charge-Pump Current Setting
The MAX9476 also allows external setting of the charge-
pump current in the PLL. Connect a resistor from SETI
to GNDP to set the PLL charge-pump current:
Charge-Pump Current = 2.4 x 1000 / (R
SET
(k
) + 1)
where R
SET
is in k
and the value of the charge-pump
current is in μA.
The loop response can be adjusted to meet individual
application requirements since the charge-pump cur-
rent and all the filter components for the VCXO loop
can be set externally.
Board Layout and Bypassing
The MAX9476
s high oscillator frequency makes proper
layout important to ensure stability. For best performance,
place components as close as possible to the device.
Digital or AC transient signals on GND can create noise
at the clock outputs. Return GND to the highest quality
ground available. Bypass V
DD
and V
DDP
with 0.1μF
and 0.001μF capacitors, placed as close to the device
as possible. Careful PC board ground layout minimizes
crosstalk between the outputs and digital inputs.
Traces must be as short as possible on LP1 and LP2
and connect the capacitors and the resistor as close as
possible to the device.
Chip Information
TRANSISTOR COUNT: 7512
PROCESS: CMOS
DampingFactor
R
2
I
N
C
SETI
=
×
×
×
1
1
8832
M
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
_______________________________________________________________________________________
7
R1
C1
C2
LP1
LP2
Figure 1. Typical Loop Filter
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相關代理商/技術參數(shù)
參數(shù)描述
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