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參數(shù)資料
| 型號： | MAX9472 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Multiple-Output Clock Generators with Dual PLLs and OTP |
| 中文描述： | 多輸出時鐘發(fā)生器，提供雙PLL和OTP |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 3400K |
| 代理商： | MAX9472 |
M
generates the SCL clock that synchronizes the data
transfer. The SDA line operates as both an input and an
open-drain output. A pullup resistor, typically 4.7k
, is
required on SDA. The SCL line operates only as an
input. A pullup resistor, typically 4.7k
, is required on
SCL if there are multiple masters on the 2-wire bus, or if
the master in a single-master system has an open-drain
SCL output. Figure 2 is the I
2
C timing diagram.
Multiple-Output Clock Generators with
Dual PLLs and OTP
8
_______________________________________________________________________________________
FS2
FS1
FS0
FREQUENCY (MHz)
AUDIO FREQUENCIES
Open
Open
Open
Low
Low
Low
High
High
High
Open
Open
Open
High
VIDEO FREQUENCIES
Low
Low
Low
Open
Open
Open
Open
Open
Open
Open
Open
Open
Low
Low
Low
Low
Open
Low
High
High
Open
Low
High
Open
Low
High
Open
Low
High
4.096
6.144
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
9.216
16.9344
18.4320
33.8688
36.864
Low
Low
Low
Low
High
Open
74.1758241
74.25
54.054
High
X
X
Disable three-level
pins and enable I
2
C
Table 2. MAX9471/MAX9472 Frequency
Selection at CLK2
A4
A3
A2
A1
FREQUENCY (MHz)
AUDIO FREQUENCIES
0
0
1
1
0
0
1
1
0
0
1
1
0
VIDEO FREQUENCIES
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4.096
6.144
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
9.216
16.9344
18.4320
33.8688
36.864
1
1
1
1
1
1
1
0
1
74.1758241
74.25
54.054
Table 3. MAX9471 I
2
C Frequency
Selection at CLK2 (FS2 = High)
SDA
SCL
t
HD, STA
t
R
t
HIGH
t
SU, DAT
t
LOW
t
F
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
t
HD, DAT
t
SU, STO
t
SU, STA
t
HD, STA
t
BUF
Figure 2. I
2
C Timing Diagram
*MAX9472 can be programmed to FS2 = open settings only.
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