參數(shù)資料
型號(hào)： MAX9452EHJ
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： High-Precision Clock Generators with Integrated VCXO
中文描述： 9452 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 5 X 5 MM, 1 MM HEIGHT, MS-026-AAA-HD, TQFP-32
文件頁數(shù)： 12/18頁
文件大?。?/td> 323K
代理商： MAX9452EHJ
M
High-Precision Clock Generators
with Integrated VCXO
12
______________________________________________________________________________________
SMBCLK
A
B
C
D
E
F
G
H
I
J
K
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 6. SMBus Read Timing Diagram
t
CSS
t
CSH
f
SCL
t
CSW
CS
SCLK
DIN
t
DS
t
DS
D0
D1
D14
D15
Figure 7. SPI Write Operation Timing Diagram
SLK
SDA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER ADDRESS
REGISTER DATA
CS
Figure 8. SPI Register Address and Data Configuration Function Setting Tables
SPI Interface
The SPI interface is activated when AD0 = AD1 = high.
The SPI port is a write-only interface, and it uses the
three inputs:
CS
, SCL, and SDA. Bit D15 is always zero,
indicating the write-only mode, as shown in Figure 5.
D14–D8 are the register address bits and D7–D0 are
the data bits. In Table 4, the register address mapping
is still valid, except the first address bit on the left is not
used. D14 is the MSB of the address, and D7 is the
MSB of the data. D15–D0 are sent with MSB (D15) first.
The maximum SCL frequency is 2MHz.
To perform a write, set D15 = 0, drive
CS
low, toggle
SCL to latch SDA data on the rising edge, then drive
CS
high after 16 SCL cycles for two SCL cycles to sig-
nal the boundary of a 16-bit word (Figure 5). SCL must
be low when
CS
falls at the start of a transmission.
Switching of SCL and SDA is ignored unless
CS
is low.
Figure 7 shows the SPI write operation timing diagram
and Figure 8 shows SPI register address and data con-
figuration function setting tables.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9452EHJ+ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9452EHJ+T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9452EHJ-T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High-Precision Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX9471ETP 制造商:Maxim Integrated Products 功能描述:MULTIPLE OUTPUT CLOCK GENERATOR WIT - Rail/Tube
MAX9471ETP+ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multiple Output Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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