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參數(shù)資料
| 型號(hào)： | MAX944MJD |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125 |
| 中文描述： | QUAD COMPARATOR, 3000 uV OFFSET-MAX, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 165K |
| 代理商： | MAX944MJD |
M
Output S tage Circ uitry
The MAX941/MAX942/MAX944 contain a current-driven
output stage as shown in Figure 4. During an output
transition, I
SOURCE
or I
SINK
is pushed or pulled to the
output pin. The output source or sink current is high
during the transition, creating a rapid slew rate. Once
the output voltage reaches V
OH
or V
OL
, the source or
sink current decreases to a small value, capable of
maintaining the V
OH
or V
OL
static condition. This signifi-
cant decrease in current conserves power after an out-
put transition has occurred.
One consequence of a current-driven output stage is a
linear dependence between the slew rate and the load
capacitance. A heavy capacitive load will slow down a
voltage output transition. This can be useful in noise-
sensitive applications where fast edges may cause
interference.
__________Applic ations Information
Circ uit Layout and Bypassing
The high gain bandwidth of the MAX941/MAX942/
MAX944 requires design precautions to realize the
comparators’ full high-speed capability. The recom-
mended precautions are:
1) Use a printed circuit board with a good, unbro-
ken, low-inductance ground plane.
2) Place a decoupling capacitor (a 0.1μF ceramic
capacitor is a good choice) as close to V+ as
possible.
3) Pay close attention to the decoupling capacitor’s
bandwidth, keeping leads short.
4) On the inputs and outputs, keep lead lengths
short to avoid unwanted parasitic feedback
around the comparators.
5) Solder the device directly to the printed circuit
board instead of using a socket.
High-S peed, Low-Power, 3V /5V,
Rail-to-Rail S ingle-S upply Comparators
8
_______________________________________________________________________________________
V
OH
t
LPW
OUT
t
LPD
t
PD
V+
0V
V+
0V
V+
2
V+
2
V
OL
LATCH
DIFFERENTIAL
INPUT
VOLTAGE
V
OS
t
H
t
S
Figure 2. MAX941 Timing Diagram with Latch Operator
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