參數(shù)資料
型號(hào): MAX9386EUP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
中文描述: 5 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20
封裝: 4.40 MM, TSSOP-20
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 247K
代理商: MAX9386EUP
M
Detailed Description
The MAX9386/MAX9387/MAX9388 are fully differential,
high-speed, and low-jitter ECL/PECL muxes with output
buffer(s). The devices are designed for clock-and-data
distribution applications, and feature extremely low
propagation delays (318ps, typ) and output-to-output
skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a
single output buffer. The MAX9387 is a 5:1 mux with
dual output buffers, and is intended for use in redun-
dant systems. The MAX9388 is a 4:1 mux with a single
output buffer, and is pin compatible with the
MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function on the MAX9386/
MAX9387. The MAX9388 has two select inputs, SEL0
and SEL1
(
see Tables 1 and 2). The mux select inputs
are compatible with ECL/PECL logic, and are internally
referenced to the on-chip output V
BB,
nominally V
CC
-
1.425V. The select inputs accept signals between V
CC
and V
EE
. Internal 120k
pulldowns to V
EE
ensure a low
default condition if the select inputs are left open,
selecting the D0,
D0
input.
The differential inputs D,
D
can be configured to accept
a single-ended signal when the unused complementary
input is connected to the on-chip reference voltage
V
BB.
The reference output voltages, V
BB1
and V
BB2,
provide the reference voltage for single-ended opera-
tion for each mux. A single-ended input of at least V
BB
_
±100mV or a differential input of at least 100mV switches
the outputs to the V
OH
and V
OL
levels specified in the
DC Electrical Characteristics.
The maximum magnitude
of the differential input from D to
D
is
±
3.0V. This limit
also applies to the difference between a single-ended
input and any reference voltage input.
Specifications for the high and low voltages of a differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
Single-Ended Operation
The recommended supply voltage for single-ended
operation is 3.0V to 5.5V. The differential inputs (D,
D
)
can be configured to accept single-ended inputs when
operating at supply voltages greater than 2.725V. In
single-ended mode operation, the unused complemen-
tary input needs to be connected to the on-chip refer-
ence voltage, V
BB
, as a reference. For example, the
differential D,
D
input is converted to a noninverting,
single-ended input by connecting V
BB
to
D
and con-
necting the single-ended input to D. Similarly, an invert-
ing input is obtained by connecting V
BB
to D and
connecting the single-ended input to
D
. With a differen-
tial input configured as single ended (using V
BB
), the
single-ended input can be driven to V
CC
or V
EE
or with
a single-ended LVPECL/LVECL signal.
In single-ended mode operation, a user must ensure
that the supply voltage (V
CC
- V
EE
) is greater than
2.725V. This is because the input high minimum level
must be at (V
EE
+ 1.2V) or higher for proper operation.
The reference voltage, V
BB
, must be at least (V
EE
+
1.2V) for the same reason because it becomes the high-
level input when a single-ended input swings below it.
The minimum V
BB
output for the MAX9386/MAX9387/
MAX9388 is (V
CC
- 1.38V). Substituting the minimum
V
BB
output for (V
BB
= V
EE
+ 1.2V) results in a minimum
supply (V
CC
- V
EE
) of 2.725V. Rounding up to standard
supplies gives the recommended single-ended operat-
ing supply ranges (V
CC
- V
EE
) of 3.0V to 5.5V.
When using the V
BB
reference output, bypass it with a
0.01μF ceramic capacitor to V
CC
. If not used, leave it
open. The V
BB
reference can source or sink a total of
0.5mA (shared between V
BB1
and V
BB2
), which is suffi-
cient to drive five inputs.
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
10
______________________________________________________________________________________
Table 1. Mux Select Input Truth Table for
MAX9386/MAX9387
SEL2
L or open
L or open
L or open
L or open
H
SEL1
L or open
L or open
H
H
X
SEL0
L or open
H
L or open
H
X
DATA OUTPUT
D0*
D1
D2
D3
D4
*
Default output when SEL0, SEL1, and SEL2 are left open.
SEL1
SEL0
DATA OUTPUT
L or open
L or open
H
H
L or open
H
L or open
H
D0*
D1
D2
D3
*
Default output when SEL0 and SEL1 are left open.
Table 2. Mux Select Input Truth Table for
MAX9388
相關(guān)PDF資料
PDF描述
MAX9387 Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
MAX9387EEG Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
MAX9388 Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
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MAX9388EUP Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
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