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參數(shù)資料
型號(hào): MAX9378EUA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 0K
描述: IC TRANSLATOR DIFF 8UMAX
標(biāo)準(zhǔn)包裝: 2,500
邏輯功能: 變換器
位數(shù): 1
輸入類型: AnyLevel?
輸出類型: LVDS
通道數(shù): 1
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 是/是
傳輸延遲(最大): 0.6ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Applications Information
LVPECL Output Termination (MAX9377)
Terminate the MAX9377 LVPECL outputs with 50
to
(VCC - 2V) or use equivalent Thevenin terminations.
Terminate OUT and OUT with identical termination on
each for low output distortion. When a single-ended
signal is taken from the differential output, terminate
both OUT and OUT. Ensure that output currents do not
exceed the current limits as specified in the Absolute
Maximum Ratings. Under all operating conditions, the
device’s total thermal limits should be observed.
LVDS Output Termination (MAX9378)
The MAX9378 LVDS outputs are current-steering
devices; no output voltage is generated without a termi-
nation resistor. The termination resistors should match
the differential impedance of the transmission line.
Output voltage levels are dependent upon the value of
the termination resistor. The MAX9378 is optimized for
point-to-point communication with the 100
termination
resistor at the receiver inputs. Termination resistance
values may range between 90
and132, depending
on the characteristic impedance of the transmission
medium.
Supply Bypassing
Bypass VCC to ground with high-frequency surface-
mount ceramic 0.1F and 0.01F capacitors. Place the
capacitors as close to the device as possible with the
0.01F capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
MAX9377/MAX9378
Anything-to-LVPECL/LVDS Translators
with Pin-Selectable Divide-by-Four
_______________________________________________________________________________________
7
VCM (MAX) = VCC - 0.05V
VCC
GND
VID
VCM (MIN) = 0.05V
VID
Figure 1. Differential Input Definition
80%
OUT - OUT
20%
80%
0V
tF
tR
DRV
OUT
RL / 2
VOD
VOD(+)
VOD(-)
VOS
GND
CL
Figure 2. LVDS Output Load and Transition Times
tPHL
tPLH
80%
20%
80%
DIFFERENTIAL OUTPUT
WAVEFORM
VID OR (VIH - VIL)
VOD OR (VOH - VOL)
+VOD OR +(VOH - VOL)
-VOD OR -(VOH - VOL)
0V DIFFERENTIAL
VOH
VOL
0V DIFFERENTIAL
IN
OUT
OUT - OUT
tF
tR
Figure 3. Differential Input-to-Output Propagation Delay Timing
Diagram
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