參數(shù)資料
型號: MAX9376EUB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: LVDS/Anything-to-LVPECL/LVDS Dual Translator
中文描述: DUAL LVDS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO10
封裝: USOP-10
文件頁數(shù): 6/7頁
文件大?。?/td> 151K
代理商: MAX9376EUB
M
LVDS/Anything-to-LVPECL/LVDS Dual Translator
6
_______________________________________________________________________________________
Applications Information
LVPECL Output Termination
Terminate the MAX9376 LVPECL outputs with 50
to
(V
CC
- 2V) or use equivalent Thevenin terminations.
Terminate OUT1 and
OUT1
with identical termination
on each for low output distortion. When a single-ended
signal is taken from the differential output, terminate
both OUT1 and
OUT1
.
Ensure that output currents do not exceed the current
limits as specified in the
Absolute Maximum Ratings
.
Under all operating conditions, the device
s total ther-
mal limits should be observed.
LVDS Output Termination
The MAX9376 LVDS outputs are current-steering
devices; no output voltage is generated without a termi-
nation resistor. The termination resistors should match
the differential impedance of the transmission line.
Output voltage levels are dependent upon the value of
the termination resistor. The MAX9376 is optimized for
point-to-point interface with 100
termination resistors
at the receiver inputs. Termination resistance values
may range between 90
and132
, depending on the
characteristic impedance of the transmission medium.
Supply Bypassing
Bypass V
CC
to ground with high-frequency surface-
mount ceramic 0.1μF and 0.01μF capacitors. Place the
capacitors as close to the device as possible with the
0.01μF capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
V
CM
(MAX)
V
CC
GND
V
ID
V
CM
(MIN)
V
ID
80%
OUT2 - OUT2
20%
20%
80%
0V
t
F
t
R
DRV
OUT2
OUT2
R
L
/ 2
R
L
/ 2
VOD
VOD(+)
VOD(-)
VOS
GND
C
L
C
L
Figure 1. Input Definition
t
PHL
t
PLH
80%
20%
20%
80%
DIFFERENTIAL OUTPUT
WAVEFORM
V
ID
OR (V
IH
- V
IL
)
V
OD
OR (V
OH
- V
OL
)
+V
OD
OR +(V
OH
- V
OL
)
-V
OD
OR -(V
OH
- V
OL
)
0V DIFFERENTIAL
V
OH
V
OL
0V DIFFERENTIAL
IN
IN
OUT
OUT
OUT - OUT
t
F
t
R
Figure 2. LVDS Output Load and Transition Times
Figure 3. Differential Input-to-Output Propagation Delay Timing
Diagram
Chip Information
TRANSISTOR COUNT: 614
PROCESS: Bipolar
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9376EUB+ 功能描述:轉(zhuǎn)換 - 電壓電平 Single LVDS/Anything To-LVPECL/LVDS RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MAX9376EUB+T 功能描述:轉(zhuǎn)換 - 電壓電平 Single LVDS/Anything To-LVPECL/LVDS RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MAX9376EUB-T 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
MAX9377EUA 功能描述:轉(zhuǎn)換 - 電壓電平 RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
MAX9377EUA+ 制造商:Maxim Integrated Products 功能描述:ANYTHING-TO-LVPECL/LVDS TRANSLATOR WITH PIN-SELECTABLE DIVID - Rail/Tube