- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗2089 > MAX9375EUA+T (Maxim Integrated Products)IC XLATR DIFF 1CH 8UMAX PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX9375EUA+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/6闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC XLATR DIFF 1CH 8UMAX |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 閭忚集鍔熻兘锛� | 璁婃彌鍣� |
| 浣嶆暩(sh霉)锛� | 1 |
| 杓稿叆椤炲瀷锛� | AnyLevel? |
| 杓稿嚭椤炲瀷锛� | LVPECL |
| 閫氶亾鏁�(sh霉)锛� | 1 |
| 杓稿嚭/閫氶亾鏁�(sh霉)鐩細 | 1 |
| 宸垎 - 杓稿叆:杓稿嚭锛� | 鏄�/鏄� |
| 鍌宠几寤堕伈锛堟渶澶э級锛� | 0.6ns |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | * |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | * |
| 鍖呰锛� | * |
Applications Information
Output Termination
Terminate the outputs with 50
to (VCC - 2V) or use
equivalent Thevenin terminations. Terminate OUT and
OUT with identical termination on each for low-output
distortion. When a single-ended signal is taken from the
differential output, terminate both OUT and OUT. Ensure
that output currents do not exceed the current limits as
specified in the Absolute Maximum Ratings. Under all
operating conditions, the device鈥檚 total thermal limits
should be observed.
Supply Bypassing
Bypass VCC to ground with high-frequency surface-
mount ceramic 0.1F and 0.01F capacitors. Place the
capacitors as close to the device as possible with the
0.01F capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
MAX9375
Single LVDS/Anything-to-LVPECL Translator
_______________________________________________________________________________________
5
VCM (MAX) = VCC - 0.05V
VCC
GND
VID
VCM (MIN) = 0.05V
VID
Figure 1. Input Definitions
Chip Information
TRANSISTOR COUNT: 614
PROCESS: Bipolar
80%
OUT - OUT
20%
80%
0V DIFFERENTIAL
tF
tR
VID
0V DIFFERENTIAL
tPLH
tPHL
VOH
VOL
VOH - VOL
DIFFERENTIAL OUTPUT
WAVEFORM
IN
OUT
IN
OUT
Figure 2. Differential Input-to-Output Propagation Delay Timing
Diagram
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX9376EUB+T | IC TRANSLATOR DUAL 10-UMAX |
| MAX9378EUA+ | IC TRANSLATOR SGL 8-UMAX |
| MAX9406ETM+ | IC DVI/HDMI LVL SHIFTR 48TQFN-EP |
| MAX941ESA+ | IC COMPARATOR R-R 8-SOIC |
| MAX9471ETP+T | IC MULTI-PURPOSE CLK GEN 20-TQFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX9376EUB | 鍔熻兘鎻忚堪:LVDS 鎺ュ彛闆嗘垚闆昏矾 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 婵€鍕�(l矛)鍣ㄦ暩(sh霉)閲�:4 鎺ユ敹姗�(j墨)鏁�(sh霉)閲�:4 鏁�(sh霉)鎿�(j霉)閫熺巼:155.5 Mbps 宸ヤ綔闆绘簮闆诲:5 V 鏈€澶у姛鐜囪€楁暎:1025 mW 鏈€澶у伐浣滄韩搴�:+ 85 C 灏佽 / 绠遍珨:SOIC-16 Narrow 灏佽:Reel |
| MAX9376EUB+ | 鍔熻兘鎻忚堪:杞�(zhu菐n)鎻� - 闆诲闆诲钩 Single LVDS/Anything To-LVPECL/LVDS RoHS:鍚� 鍒堕€犲晢:Micrel 椤炲瀷:CML/LVDS/LVPECL to LVCMOS/LVTTL 鍌虫挱寤堕伈鏅�(sh铆)闁�:1.9 ns 闆绘簮闆绘祦:14 mA 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MLF-8 |
| MAX9376EUB+T | 鍔熻兘鎻忚堪:杞�(zhu菐n)鎻� - 闆诲闆诲钩 Single LVDS/Anything To-LVPECL/LVDS RoHS:鍚� 鍒堕€犲晢:Micrel 椤炲瀷:CML/LVDS/LVPECL to LVCMOS/LVTTL 鍌虫挱寤堕伈鏅�(sh铆)闁�:1.9 ns 闆绘簮闆绘祦:14 mA 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MLF-8 |
| MAX9376EUB-T | 鍔熻兘鎻忚堪:LVDS 鎺ュ彛闆嗘垚闆昏矾 RoHS:鍚� 鍒堕€犲晢:Texas Instruments 婵€鍕�(l矛)鍣ㄦ暩(sh霉)閲�:4 鎺ユ敹姗�(j墨)鏁�(sh霉)閲�:4 鏁�(sh霉)鎿�(j霉)閫熺巼:155.5 Mbps 宸ヤ綔闆绘簮闆诲:5 V 鏈€澶у姛鐜囪€楁暎:1025 mW 鏈€澶у伐浣滄韩搴�:+ 85 C 灏佽 / 绠遍珨:SOIC-16 Narrow 灏佽:Reel |
| MAX9377EUA | 鍔熻兘鎻忚堪:杞�(zhu菐n)鎻� - 闆诲闆诲钩 RoHS:鍚� 鍒堕€犲晢:Micrel 椤炲瀷:CML/LVDS/LVPECL to LVCMOS/LVTTL 鍌虫挱寤堕伈鏅�(sh铆)闁�:1.9 ns 闆绘簮闆绘祦:14 mA 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MLF-8 |
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