
Applications Information
Output Termination
Terminate the outputs with 50
to (VCC - 2V) or use
equivalent Thevenin terminations. Terminate OUT and
OUT with identical termination on each for low-output
distortion. When a single-ended signal is taken from the
differential output, terminate both OUT and OUT. Ensure
that output currents do not exceed the current limits as
specified in the Absolute Maximum Ratings. Under all
operating conditions, the device’s total thermal limits
should be observed.
Supply Bypassing
Bypass VCC to ground with high-frequency surface-
mount ceramic 0.1F and 0.01F capacitors. Place the
capacitors as close to the device as possible with the
0.01F capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
MAX9375
Single LVDS/Anything-to-LVPECL Translator
_______________________________________________________________________________________
5
VCM (MAX) = VCC - 0.05V
VCC
GND
VID
VCM (MIN) = 0.05V
VID
Figure 1. Input Definitions
Chip Information
TRANSISTOR COUNT: 614
PROCESS: Bipolar
80%
OUT - OUT
20%
80%
0V DIFFERENTIAL
tF
tR
VID
0V DIFFERENTIAL
tPLH
tPHL
VOH
VOL
VOH - VOL
DIFFERENTIAL OUTPUT
WAVEFORM
IN
OUT
IN
OUT
Figure 2. Differential Input-to-Output Propagation Delay Timing
Diagram