參數(shù)資料
型號: MAX9372EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/9頁
文件大小: 0K
描述: IC TRANSLATOR 8-UMAX
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
邏輯功能: 變換器
位數(shù): 2
輸入類型: LVTTL,TTL
輸出類型: LVPECL,PECL
通道數(shù): 2
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/是
傳輸延遲(最大): 0.27ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 帶卷 (TR)
Detailed Description
The MAX9370/MAX9371/MAX9372 LVTTL/TTL-to-differ-
ential LVPECL/PECL translators are designed for high-
speed communication signal and clock driver
applications. The MAX9370/MAX9372 are dual LVTTL-
to-LVPECL/PECL translators that operate in excess of
1GHz. The MAX9371 is a single translator. The
MAX9370/MAX9371 operate over a wide 3.0V to 5.25V
supply range, allowing high-performance clock or data
distribution in systems with a nominal 3.3V or 5.0V sup-
ply. The MAX9372 is optimized for 3.0V to 3.6V opera-
tion. These devices feature low 270ps propagation
delay and 40ps peak-to-peak deterministic jitter.
Inputs and Outputs
The MAX9370/MAX9371/MAX9372 inputs accept stan-
dard LVTTL/TTL levels. The input has pullup circuitry that
drives the outputs to a differential high if the inputs are
open. The outputs are differential LVPECL/PECL levels.
Applications Information
Output Termination
Terminate outputs with 50
to VCC - 2V or use an equiv-
alent Thevenin termination. Use the same terminate on
each output for the lowest output-to-output skew. When a
single-ended signal is taken from a differential output,
terminate both outputs. For example, if Q is used as a
single-ended output, terminate both Q and Q.
MAX9370/MAX9371/MAX9372
LVTTL/TTL-to-Differential LVPECL/PECL
Translators
_______________________________________________________________________________________
5
Pin Description for the MAX9370/MAX9372
PIN
SO
MAX
SOT23
NAME
FUNCTION
1
8
Q0
Noninverting Differential LVPECL/PECL Output 0. Typically terminate with 50
resistor to VCC - 2V.
27
Q0
Inverting Differential LVPECL/PECL Output 0. Typically terminate with 50
resistor to VCC - 2V.
3
6
Q1
Noninverting Differential LVPECL/PECL Output 1. Typically terminate with 50
resistor to VCC - 2V.
45
Q1
Inverting Differential LVPECL/PECL Output 1. Typically terminate with 50
resistor to VCC - 2V.
52
GND
Ground. Provide a low-impedance connection to ground plane.
6
4
D1
LVTTL/TTL Input 1. LVTTL/TTL input for translator corresponding to output Q1 and
Q1.
7
3
D0
LVTTL/TTL Input 0. LVTTL/TTL input for translator corresponding to output Q0 and
Q0.
81
VCC
Positive Supply Voltage. Bypass VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Pin Description for the MAX9371
PIN
SO
MAX
SOT23
NAME
FUNCTION
1, 4, 6
4, 5, 8
N.C.
No Connection. No internal connection.
2
7
Q
Noninverting Differential LVPECL/PECL Output. Typically terminate with 50
resistor to VCC - 2V.
36
Q
Inverting Differential LVPECL/PECL Output. Typically terminate with 50
resistor to VCC - 2V.
52
GND
Ground. Provide a low-impedance connection to ground plane.
7
3
D
LVTTL/TTL Input
81
VCC
Positive Supply Voltage. Bypass VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
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