參數(shù)資料
型號: MAX9360
廠商: Maxim Integrated Products, Inc.
英文描述: LVTTL/TTL/CMOS-to-Differential LVECL/ ECL Translators
中文描述: LVTTL/TTL/CMOS至差分LVECL/ECL轉(zhuǎn)換器
文件頁數(shù): 7/9頁
文件大小: 159K
代理商: MAX9360
Detailed Description
The MAX9360/MAX9361 are low-skew, single LVTTL/
CMOS/TTL-to-differential LVECL/ECL translators
designed for high-speed signal and clock driver appli-
cations. For interfacing to LVTTL/TTL/CMOS input sig-
nals, these devices operate over a 3.0V to 5.5V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal 3.3V or 5.0V supply. For
interfacing to differential LVECL/ECL output signals,
these devices operate from a -2.375V to -5.5V supply.
The MAX9360 is a 3.3V LVTTL/CMOS-to-LVECL/ECL
translator that operates at typical speeds of 3GHz. The
MAX9361 is a 5V TTL/CMOS-to-LVECL/ECL translator that
operates at typical speeds of 1.3GHz. Both devices can
be used to drive either LVECL devices or standard ECL
devices with a negative supply range of -2.375V to -5.5V.
Input
The MAX9360/MAX9361 inputs accept standard LVTTL/
TTL/CMOS levels. The input has pullup circuitry that dri-
ves the outputs to a differential high if the inputs are open.
Differential Output
Output levels are referenced to GND and are considered
ECL or LVECL, depending on the level of the V
EE
supply.
With GND connected to zero and V
EE
at -4.2V to -5.5V,
the outputs are ECL. The outputs are LVECL when GND is
connected to zero and V
EE
is at -2.375V to -3.8V.
Applications Information
Supply Bypassing
Bypass V
CC
and V
EE
to ground with high-frequency
surface-mount ceramic 0.1μF and 0.01μF capacitors in
parallel as close to the device as possible, with the
0.01μF value capacitor closest to the device. Use multi-
ple parallel vias for low inductance.
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9360/MAX9361. Connect each signal
of a differential output to a 50
characteristic imped-
ance trace. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by main-
taining the 50
characteristic impedance through con-
nectors and across cables. Reduce skew within a
differential pair by matching the electrical length of the
traces.
On the MAX9360, if the input edge rate approaches the
electrical length of the interconnect, then controlled-
impedance transmission lines should be used for the
input traces.
Output Termination
Terminate outputs through 50
to -2V or use an equiva-
lent Thevenin termination. Terminate both outputs and
use the same termination on each for the lowest output-
to-output skew. When a single-ended signal is taken
from a differential output, terminate both outputs. For
example, if Q is used as a single-ended output, termi-
nate both Q and
Q
.
Ensure that the output currents do not exceed the con-
tinuous safe output current limit or surge output current
limit as specified in the
Absolute Maximum Ratings
table. Under all operating conditions, the device
s total
thermal limits should be observed.
Chip Information
TRANSISTOR COUNT: 330
PROCESS: Bipolar
M
LVTTL/TTL/CMOS-to-Differential LVECL/
ECL Translators
_______________________________________________________________________________________
7
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