參數(shù)資料
型號: MAX9325EQI+
廠商: Maxim Integrated Products
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC CLK/DATA BUFF MUX 2:8 28-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 39
類型: 扇出緩沖器(分配),多路復(fù)用器,數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/是
輸入: HSTL,LVECL,LVPECL
輸出: LVECL,LVPECL
頻率 - 最大: 700MHz
電源電壓: 2.375 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS—QFN Package
((VCC - VEE) = 2.375V to 3.8V, RL = 50 ±1% to VCC - 2V, fIN ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Note 7)
-40
°C
+25
°C
+85
°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Differential
Input-to-Output
Delay
tPLHD
tPHLD
Figure 2
250
575
298
553
309
576
ps
Single-Ended
Input-to-Output
Delay
tPLH
tPHL
Figure 3 (Note 8)
253
581
310
586
324
606
ps
Output-to-
Output Skew
tSKOO
(Note 9)
50
ps
Part-to-Part
Skew
tSKPP
Differential input
(Note 10)
192
215
218
ps
Added Random
Jitter
tRJ
fIN = 0.5GHz
clock pattern
(Note 11)
1.5
psRMS
Added
Deterministic
Jitter
tDJ
fIN = 1.0Gbps,
2E
23 - 1 PRBS
pattern (Note 11)
95
psP-P
Switching
Frequency
fMAX
VOH - VOL
300mV clock
pattern
1.5
GHz
Output Rise/Fall
Time (20% to
80%)
tR, tF
Figure 2
97
411
104
210
111
232
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Note 4:
Single-ended input operation using VBB is limited to (VCC - VEE) = 3.0V to 3.8V.
Note 5:
Use VBB only for inputs that are on the same device as the VBB reference.
Note 6:
All pins open except VCC and VEE.
Note 7:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:
Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Note 9:
Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Note 10: Measured between outputs of different parts under identical condition for same-edge transition.
Note 11: Device jitter added to the input signal. Differential input signal.
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MAX9325EQI+ 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
MAX9325EQI+T 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
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