
Detailed Description
The MAX9321B low-skew differential receiver/driver is
designed for clock and data distribution. For interfacing
to differential PECL/LVPECL signals, this device oper-
ates over a +3.0V to +5.5V supply range, allowing high-
performance clock and data distribution in systems with
a nominal 3.3V or 5V supply. For differential ECL/
LVECL operation, this device operates from a -3.0V to
-5.5V supply.
Inputs
The differential input can be configured to accept a sin-
gle-ended input. This is accomplished by connecting
the on-chip reference voltage, V
BB
, to an input as a ref-
erence. For example, the differential input is converted
to a noninverting, single-ended input by connecting
V
BB
to
D
and connecting the single-ended input to D.
An inverting input is obtained by connecting V
BB
to D
and connecting the single-ended input to
D
.
When using the V
BB
reference output, bypass it with a
0.01μF ceramic capacitor to V
CC
. If the V
BB
reference
is not used, it can be left open. The V
BB
reference can
source or sink 0.5mA. Use V
BB
only for an input on the
same device as the V
BB
reference.
The maximum magnitude of the differential input from D
to
D
is 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 50k
pullup to V
CC
and a 100k
pulldown to V
EE.
The noninverting input is
biased with an 80k
pullup to V
CC
and a 60k
pull-
down to V
EE
.
Specifications for the high and low voltage of the differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously (V
ILD
cannot
be higher than V
IHD
).
Outputs
Output levels are referenced to V
CC
and are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the V
CC
supply. With V
CC
connected to a posi-
tive supply and V
EE
connected to GND, the output is
PECL/LVPECL. The output is ECL/LVECL when V
CC
is
connected to GND and V
EE
is connected to a negative
supply.
A single-ended input of at least V
BB
±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the V
OH
and V
OL
levels specified in the
DC Electrical
Characteristics
table.
Applications Information
Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1μF and 0.01μF capacitors in parallel as
close to the device as possible, with the 0.01μF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance. When using the V
BB
reference output, bypass it with a 0.01μF ceramic
capacitor to V
CC
(if the V
BB
reference is not used, it
can be left open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9321B. Connect each signal of a differ-
ential input or output to a 50
characteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50
characteristic impedance through connectors and
M
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
6
_______________________________________________________________________________________
Pin Description
PIN
1
2
3
NAME
N.C.
D
D
FUNCTION
No Connection
Noninverting Differential Input. 80k
pullup to V
CC
, 60k
pulldown to V
EE
.
Inverting Differential Input. 50k
pullup to V
CC
and 100k
pulldown to V
EE
.
Reference Output Voltage. Connect to the inverting or noninverting input to provide a reference for single-
ended operation. When used, bypass with a 0.01μF ceramic capacitor to V
CC
; otherwise leave open.
Negative Supply Voltage
Inverting Output. Typically terminate with 50
resistor to V
CC
- 2V.
Noninverting Output. Typically terminate with 50
resistor to V
CC
- 2V.
Positive Supply Voltage. Bypass from V
CC
to V
EE
with 0.1μF and 0.01μF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
4
V
BB
5
6
7
V
EE
Q
Q
8
V
CC