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參數(shù)資料
| 型號： | MAX9321-MAX9321A |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Differential LVPECL/LVECL/HSTL Receiver/Drivers |
| 中文描述： | 差分LVPECL / LVECL / HSTL接收器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 178K |
| 代理商： | MAX9321-MAX9321A |
Detailed Description
The MAX9321/MAX9321A are low-skew differential
receiver/drivers designed for clock and data distribu-
tion. For interfacing to differential HSTL and LVPECL
signals, these devices operate over a +2.25V to +3.8V
supply range, allowing high-performance clock and
data distribution in systems with a nominal +2.5V or
+3.3V supply. For differential LVECL operation, these
devices operate from a -2.25V to -3.8V supply.
Inputs
The differential input can be configured to accept a sin-
gle-ended input when operating at approximately V
CC
-
V
EE
= 3.0V to 3.8V. This is accomplished by connect-
ing the on-chip reference voltage, V
BB
, to an input as a
reference. For example, the differential D,
D
input is
converted to a noninverting, single-ended input by con-
necting V
BB
to
D
and connecting the single-ended
input to D. An inverting input is obtained by connecting
V
BB
to D and connecting the single-ended input to
D
.
With the differential input configured as single ended
(using V
BB
), the single-ended input can be driven to
V
CC
and V
EE
or with a single-ended LVPECL/LVECL
signal.
When the differential input is configured as a single-
ended input (using V
BB
), the approximate supply range
is V
CC
- V
EE
= 3.0V to 3.8V. This is because one of the
inputs must be V
EE
+ 1.2V or higher for proper opera-
tion of the input stage. V
BB
must be at least V
EE
+ 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
mum V
BB
= V
EE
+ 1.2V.
The minimum V
BB
output is V
CC
- 1.510V. Substituting
the minimum V
BB
into V
BB
= V
EE
+ 1.2V results in a
minimum supply of 2.71V. Rounding up to a standard
supply gives the single-ended operating supply range
of V
CC
- V
EE
= 3.0V to 3.8V.
M
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
_______________________________________________________________________________________
7
(CONNECTED TO D)
V
IL
V
IH
V
BB
V
OH
- V
OL
V
OH
V
OL
Q
Q
D
D
Figure 1. Switching with Single-Ended Input
0 (DIFFERENTIAL)
80%
20%
80%
20%
0 (DIFFERENTIAL)
V
OH
- V
OL
V
IHD
- V
ILD
V
IHD
V
ILD
V
OH
V
OL
Q
Q
t
PLHD
t
PHLD
t
R
t
F
D
D
(Q) - (Q)
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
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參數(shù)描述 |
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| MAX9322ECY+ | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL DIVIDE-BY-1/DIVIDE-BY-2 CLOCK DRVR 52TQFP - Rail/Tube |
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| MAX9322ECY-D | 功能描述:通信集成電路 - 若干 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
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