參數(shù)資料
型號: MAX9310AEUP+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/11頁
文件大?。?/td> 0K
描述: IC CLOCK DRVR 1.0GHZ 20TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
輸入: HSTL,LVPECL
輸出: LVDS
頻率 - 最大: 1GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
MAX9310A
4
_______________________________________________________________________________________
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and
characterized over the full operating temperature range.
Note 4: Use VBB only for inputs that are on the same device as the VBB reference.
Note 5: All pins are open except VCC and GND, all outputs are loaded with 100
differentially.
Note 6: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge
transition.
Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions
for a same-edge transition.
Note 9: Device jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC - GND = 3V to 3.6V, outputs terminated with 100
±1%, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%),
VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V,
unless otherwise noted.) (Notes 1 and 6)
-40
°C
+25
°C
+85
°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Propagation
Delay CLK_,
CLK_ to Q_, Q_
tPHL,
tPLH
Figure 2
250
340
600
250
340
600
250
340
600
ps
Output-to-
Output Skew
tSKOO
(Note 7)
10
30
8
25
20
45
ps
Part-to-Part
Skew
tSKPP
(Note 8)
145
ps
Added Random
Jitter
tRJ
fIN = 1.0GHz,
clock pattern
(Note 9)
0.3
1.0
0.3
1.0
0.3
1.0
ps
(RMS)
Added
Deterministic
Jitter
tDJ
fIN = 1.0Gsps,
2
23 - 1 PRBS
pattern (Note 9)
50
60
50
60
50
60
ps
(P-P)
Operating
Frequency
fMAX
VOD
≥ 250mV
1.0
GHz
Differential
Output Rise/Fall
Time
tR/tF
20% to 80%,
Figure 2
140
205
300
140
205
300
140
205
300
ps
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
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