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參數(shù)資料
| 型號(hào)： | MAX9310AEUP+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DRVR 1.0GHZ 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類(lèi)型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
MAX9310A
6
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
Q0
Noninverting Differential Output 0. Typically terminated with 100
to Q0.
2
Q0
Inverting Differential Output 0. Typically terminated with 100
to Q0.
3
Q1
Noninverting Differential Output 1. Typically terminated with 100
to Q1.
4
Q1
Inverting Differential Output 1. Typically terminated with 100
to Q1.
5
Q2
Noninverting Differential Output 2. Typically terminated with 100
to Q2.
6
Q2
Inverting Differential Output 2. Typically terminated with 100
to Q2.
7
Q3
Noninverting Differential Output 3. Typically terminated with 100
to Q3.
8
Q3
Inverting Differential Output 3. Typically terminated with 100
to Q3.
9
Q4
Noninverting Differential Output 4. Typically terminated with 100
to Q4.
10
Q4
Inverting Differential Output 4. Typically terminated with 100
to Q4.
11
GND
Ground
12
CLKSEL
Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1,
CLK1 input. The CLKSEL threshold is equal to VBB. Internal 60k
pulldown to GND.
13
CLK0
Noninverting Differential Clock Input 0. Internal 75k
pulldown to GND.
14
CLK0
Inverting Differential Clock Input 0. Internal 75k
pullup to VCC and 75k pulldown to GND.
15
VBB
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to
VCC; otherwise, leave open.
16
CLK1
Noninverting Differential Input 1. Internal 75k
pulldown to GND.
17
CLK1
Inverting Differential Input 1. Internal 75k
pullup to VCC and 75k pulldown to GND.
18, 20
VCC
Positive Supply Voltage. Bypass VCC to GND with 0.1F and 0.01F ceramic capacitors. Place
the capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
19
EN
Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected
clock input when EN is low. Outputs are synchronously driven to a differential low state on the
falling edge of the selected clock input when EN is high. Internal 60k
pulldown to GND
(Figure 3).
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9310AEUP+ | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 1:5 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9310AEUP+T | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 1:5 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9310AEUP-T | 制造商:Maxim Integrated Products 功能描述:1:5 CLOCK DRIVER WITH SELECTABLE LVPECL INPUT - Tape and Reel |
| MAX9310EUP | 制造商:Maxim Integrated Products 功能描述:1:5 CLOCK DRIVER WITH SELECTABLE LVPECL INPUT - Bulk |
| MAX9310EUP+ | 制造商:Maxim Integrated Products 功能描述:CLOCK DRVR 2-IN LVDS 20TSSOP - Rail/Tube |
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