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參數(shù)資料
| 型號(hào)： | MAX9273GTL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER 22BIT GMSL 40TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
23
Maxim Integrated
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive
twisted-pair cable and single-ended CML to drive coaxial
cable. The output amplitude is programmable.
Input data is scrambled and then 8b/10b coded. The
deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is
the parity bit of the previous 23 or 31 bits (Figure 17).
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and GPO signals from the deserializer in the
opposite direction of the video stream. The reverse
control channel and forward video data coexist on
the same serial cable forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after start-
ing/stopping the forward serial link.
Data-Rate Selection
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKIN frequency range (Table 3). Set DRS = 1 for
a PCLKIN frequency range of 6.25MHz to 12.5MHz (32-
bit, single-input mode) or 8.33MHz to 16.66MHz (24-bit,
single-input mode). Set DRS = 0 for normal operation.
It is not recommended to use double-input mode when
DRS = 1.
Control Channel and Register Programming
The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. The FC controls the link from
either the serializer or deserializer side. The control chan-
nel between the FC and serializer or deserializer runs in
base mode or bypass mode, according to the mode-
selection (MS) input of the device connected to the FC.
Base mode is a half-duplex control channel and bypass
mode is a full-duplex control channel.
UART Interface
In base mode, the FC is the host and can access the
registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The FC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
deserializer, with the UART packets converted to I2C
by the device on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the half-duplex
default GMSL UART protocol of the serializer/deserial-
izer. The device addresses of the serializer/deserializer in
base mode are programmable. The default value is 0x80
for the serializer and 0x90 for the deserializer.
When the peripheral interface is I2C, the serializer/
deserializer convert UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
FIRST WORD
THIRD WORD
FIRST AND SECOND WORD
THIRD AND FOURTH WORD
PCLKIN
÷ 2
LATCH A
LATCH B
DIN0–DIN14
OR
DIN0–DIN10
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