
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
33
Maxim Integrated
Connect OUT- to IN- of the second deserializer. Control-
channel data is broadcast from the serializer to both
deserializers and their attached peripherals. Assign a
unique address to send control data to one deserializer.
Leave all unused IN_ pins unconnected, or connect them
to ground through 50I and a capacitor for increased
power-supply rejection. If OUT- is not used, connect
OUT- to AVDD through a 50I resistor
(Figure 30). When
there are FCs at the serializer, and at each deserializer,
only one FC can communicate at a time. Disable one
splitter control-channel link to prevent contention. Use
the DIS_REV_P or DIS_REV_N register bits to disable a
control-channel link.
Cable Type Configuration Input (CX/TP)
CX/TP determines the power-up state of the serial input.
In coax mode, CX/TP also determines which coax input
is active, along with the default device address
(Table 8).
These functions can be changed after power-up by writing
to the appropriate register bits.
Sleep Mode
The deserializer includes a sleep mode to reduce power
consumption. The device enters or exits sleep mode by a
command from a local FC or a remote FC using the con-
trol channel. Set the SLEEP bit to 1 to initiate sleep mode.
The serializer sleeps immediately after setting its SLEEP
= 1. The deserializer sleeps after serial link inactivity or
8ms (whichever arrives first) after setting its SLEEP = 1.
To wake up from the local side, send an arbitrary control-
channel command to the deserializer, wait 5ms for the
chip to power up, and then write 0 to the SLEEP register
bit to make the wake-up permanent. To wake up from the
remote side, enable serialization. To deserializer detects
the activity on the serial link and then when it locks, it
automatically sets its SLEEP register bit to 0.
Power-Down Mode
The deserializer has a power-down mode that further
reduces power consumption compared to sleep mode.
Set PWDN low to enter power-down mode. In power-
down mode, the outputs of the device remain in high
impedance. Entering power-down resets the device’s
registers. Upon exiting power-down, the state of external
pins GPIO1/BWS, GPIO0/DBL, CX / TP, I2CSEL, LCCEN,
RX /SDA /EDC, TX /SCL /ES, and MS/HVEN are latched.
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable the configuration
link. The configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
Figure 29. 2:1 Coax-Mode Splitter Connection Diagram
Figure 30. Coax-Mode Connection Diagram
Table 8. Configuration Input Map
CX/TP
FUNCTION
High
Coax+ input. Device address 0x90.
Mid
Coax- input. Device address 0x92.
Low
Twisted-pair input. Device address 0x90.
OUT+
OUT-
IN+
IN-
IN+
IN-
MAX9272
GMSL
SERIALIZER
OUT+
OUT-
IN+
IN-
AVDD
50I
MAX9272
GMSL
SERIALIZER