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參數(shù)資料
| 型號： | MAX9272GTM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSERIALIZER 28BIT GMSL 48TQFN |
| 標準包裝： | 43 |
| 系列： | * |
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MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
28
Maxim Integrated
Figure 22. START and STOP Conditions
Figure 23. Bit Transfer
Figure 24. Acknowledge
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 22). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 23). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure
24). Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the for-
ward control channel is not active (not locked). To prevent
acknowledge generation when the forward control chan-
nel is not active, set the I2CLOCACK bit low.
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1
2
8
9
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9272GTM/V+ | 功能描述:串行器/解串器 - Serdes 1.5Gbps 28-bit Coax/STP deserializr RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9272GTM/V+T | 功能描述:串行器/解串器 - Serdes 1.5Gbps 28-bit Coax/STP deserializr RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9272GTM+ | 功能描述:串行器/解串器 - Serdes 1.5Gbps 28-bit Coax/STP deserializr RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9272GTM+T | 功能描述:串行器/解串器 - Serdes 1.5Gbps 28Bit Coax/STP deserializr RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9272GTV+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:28-Bit GMSL Deserializer for Coax or STP Cable |
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